No the calculation looks okay, the problem is with the two layer board the reference plane is 60 mils or more from the trace. You can think of it like this: Transmission lines need a certain width to height ratio, if the height is increased you must also increase the width.

So you either need to decrease the height, or increase the dielectric constant of the transmission line to get a smaller width. Seeing as how four layer boards are so cheap these days it might be worth just going to a four-layer board, then a non-standard stack up but you'd have to consult with your PCB manufacturer.

Another thing is it might be difficult to maintain low inductance digital pathways with the two layer board for the MII or RMII interface (especially the 50 MHz for RMII)

No the calculation looks okay, the problem is with the two layer board the reference plane is 60 mils or more from the trace. You can think of it like this: Transmission lines need a certain width to height ratio, if the height is increased you must also increase the width.

So you either need to decrease the height, or increase the dielectric constant of the transmission line to get a smaller width. Seeing as how four layer boards are so cheap these days it might be worth just going to a four-layer board, then a non-standard stack up but you'd have to consult with your PCB manufacturer.

Another thing is it might be difficult to maintain low inductance digital pathways with the two layer board for the MII or RMII interface (especially the 50 MHz for RMII)

are these resistors for impedance matching goal? may I use something like this?

Those resistors are pull ups for the transceivers on the LAN8720A. One thing you might try if you really need a 2 layer board is keeping the traces very very short between phy and magnetics (and between magnetics and connector).