Timeline for Timing constrain the ADC to FPGA data path
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 4, 2022 at 19:06 | comment | added | Anonymous | Link to datasheet? Part numbers? | |
| Dec 4, 2022 at 14:17 | comment | added | gyuunyuu | See the ADC actually operates at a very high frequency. The datasheet of the ADC implies that it should not be fed from the FPGA clock pin but directly from the oscillator. | |
| Dec 3, 2022 at 19:28 | history | answered | Anonymous | CC BY-SA 4.0 |