There are some small problems in your code: The output Addr_in_temp_o of Ramdom_Access_memory is not connected in your testbench. So the simulation always shows the value 0 (default value of integer) at the signal Addr_in_temp_o_tb. The clocked process in Random_Access_Memory is also sensitive to Addr_i which is not needed. But the real problem is: In your testbench you permanently write (store=0) a 0 into the address 1 and you also read permanently (enable=0) from address 1. So of course you always read 0. If you zoom in at the time 0, you perhaps can see the value FF for 1 clock cycle at the read data output.

There are some small problems in your code: The output Addr_in_temp_o of Ramdom_Access_memory is not connected in your testbench. So the simulation always shows the value 0 (default value of integer) at the signal Addr_in_temp_o_tb. The clocked process in Random_Access_Memory is also sensitive to Addr_i which is not needed.

But the real problem is: In your testbench you permanently write (store=0) a 0 into the address 1 and you also read permanently (enable=0) from address 1. So of course you always read 0. If you zoom in at the time 0, you perhaps can see the value FF for 1 clock cycle at the read data output.