Timeline for Active load role on this circuit and possible uses
Current License: CC BY-SA 4.0
20 events
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| Feb 5, 2023 at 18:00 | history | tweeted | twitter.com/StackElectronix/status/1622294007383572480 | ||
| Feb 5, 2023 at 17:24 | comment | added | Sredni Vashtar | Related electronics.stackexchange.com/questions/450935/… | |
| Feb 5, 2023 at 16:48 | comment | added | G36 | As I said early the main reason why we add active load to the circuit is there is a desire to increase the voltage gain and to "remove" unwanted resistors from the integral circuit. | |
| Feb 5, 2023 at 16:37 | comment | added | tac | @G36 What I mean is, maybe the input and output impedance would be somehow worse that what is needed here. My hypothesis is that the circuit just let pass high frequencies. Again I repeat: This is just an exercise given where one has to guess a possible application for the circuit | |
| Feb 5, 2023 at 16:34 | comment | added | G36 | So what is your point? Or a problem? | |
| Feb 5, 2023 at 16:29 | comment | added | tac | @G36 I do understand that. Not all stages have to amplify voltage. Maybe if the active loads were not used, the AC resistance would be much lower and that would ruin the input and output impedance | |
| Feb 5, 2023 at 16:21 | comment | added | G36 | But do you understand that now you have a circuit with no gain? \$Av \approx \frac{R_{CA}||R_L}{R_{EA}}\$ And REA will be large and it will depend on the collector current and on the Early voltage value REA = VA/Ic. Also, the two current sources are not needed. Only one current source at the collector will do the job. | |
| Feb 5, 2023 at 15:59 | comment | added | tac | @carloc ok but suppose the ideal conditions where all is perfectly matched. Actually I'm trying to find an application for this circuit, not to design, simulate or implement it | |
| Feb 5, 2023 at 15:57 | comment | added | tac | @G36 but the active load requires the use of resistors R1 and R2 so you still need them | |
| Feb 5, 2023 at 15:56 | comment | added | tac | @ErnestoG I don't know how to use this circuit. This is just an exercise given where one has to guess a possible application for the circuit | |
| Feb 5, 2023 at 15:53 | history | edited | tac | CC BY-SA 4.0 |
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| Feb 5, 2023 at 15:42 | history | edited | tac | CC BY-SA 4.0 |
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| Feb 5, 2023 at 8:28 | comment | added | carloc | This topology is basically not-working. You have two different current souces series connected, Q1 and Q5. Two current sources can't possibly drive exactly the same current and hence the operating point point can only collapse with one of the sources saturated. You should get rid of either Q1 or Q5. | |
| Feb 5, 2023 at 8:24 | comment | added | G36 | But to get the benefits from the larger gain provided by an active load. Next stage input resistance also needs to be large. So this circuit is not suited to drive low resistance loads. And also some negative feedback is needed to "set" DC bias conditions at the desired and predictable "level". | |
| Feb 5, 2023 at 8:15 | comment | added | G36 | But the configuration shows your circuit will act more like an attenuator than an amplifier. The gain will be less than one. We are adding an active load in the IC design to increase the voltage. And we cannot use the resistors because they take a lot of space in the silicon. Thus we use transistors instead as load. | |
| Feb 5, 2023 at 7:28 | comment | added | Designalog | Do you plan to use this amplifier as standalone, or within more stages and a global feedback loop? | |
| Feb 5, 2023 at 5:25 | history | edited | tac | CC BY-SA 4.0 |
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| Feb 5, 2023 at 4:39 | history | edited | tac | CC BY-SA 4.0 |
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| S Feb 5, 2023 at 4:06 | review | First questions | |||
| Feb 5, 2023 at 5:50 | |||||
| S Feb 5, 2023 at 4:06 | history | asked | tac | CC BY-SA 4.0 |