Notice first that there are two identical structures repeated, consisting each of two PMOS, a 10k resistor, and NMOS arranged in a sort of T shape. A positive voltage on the gate of the NMOS allows current through, pulling the two PMOS gates down and effectively opening a path through their drains. This is a voltage controlled switch implemented with MOSFETs, it allows current in either direction, so it is not itself backflow prevention as you say.

Imagine for a second that the bottom of R26 is unconnected. In this modified circuit, the presence of VUSB places the full 5 volts on the NMOS gate, opening the switch and allowing VUSB to power +5V.

If you ground that same end of R26, the NMOS gate voltage will drop almost to zero due to R26 being much smaller than R25, thus cutting off VUSB from +5V. This means you can use a low voltage at this point to "supersede" the 5 volts available from VUSB, which the full circuit indeed does.

V_Ext is connected to an identical gate circuit, whose NMOS also pulls this "supersede" signal from the previous structure low. The full circuit thus gives priority to V_Ext. If Both V_Ext and VUSB are present, V_Ext is connected to +5V. If only VUSB is present and V_Ext is open, then Q5-2 will have zero volts at its gate, and R26 will be seeing an open circuit, opening the VUSB "switch", allowing VUSB to power +5V.

Edit: This circuit does actually provide backflow prevention between +5V and VUSB, now that I simulate it.

Notice first that there are two identical structures repeated, consisting each of two PMOS, a 10k resistor, and NMOS arranged in a sort of T shape. A positive voltage on the gate of the NMOS allows current through, pulling the two PMOS gates down and effectively opening a path through their drains. This is a voltage controlled switch implemented with MOSFETs.

Imagine for a second that the bottom of R26 is unconnected. In this modified circuit, the presence of VUSB places the full 5 volts on the NMOS gate, opening the switch and allowing VUSB to power +5V.

If you ground that same end of R26, the NMOS gate voltage will drop almost to zero due to R26 being much smaller than R25, thus cutting off VUSB from +5V. This means you can use a low voltage at this point to "supersede" the 5 volts available from VUSB, which the full circuit indeed does.

V_Ext is connected to an identical gate circuit, whose NMOS also pulls this "supersede" signal from the previous structure low. The full circuit thus gives priority to V_Ext. If Both V_Ext and VUSB are present, V_Ext is connected to +5V. If only VUSB is present and V_Ext is open, then Q5-2 will have zero volts at its gate, and R26 will be seeing an open circuit, opening the VUSB "switch", allowing VUSB to power +5V.

Edit: This circuit does actually provide backflow prevention between +5V and VUSB, now that I simulate it.

Notice first that there are two identical structures repeated, consisting each of two PMOS, a 10k resistor, and NMOS arranged in a sort of T shape. A positive voltage on the gate of the NMOS allows current through, pulling the two PMOS gates down and effectively opening a path through their drains. This is a voltage controlled switch implemented with MOSFETs, it allows current in either direction, so it is not itself backflow prevention as you say.

Imagine for a second that the bottom of R26 is unconnected. In this modified circuit, the presence of VUSB places the full 5 volts on the NMOS gate, opening the switch and allowing VUSB to power +5V.

If you ground that same end of R26, the NMOS gate voltage will drop almost to zero due to R26 being much smaller than R25, thus cutting off VUSB from +5V. This means you can use a low voltage at this point to "supersede" the 5 volts available from VUSB, which the full circuit indeed does.

V_Ext is connected to an identical gate circuit, whose NMOS also pulls this "supersede" signal from the previous structure low. The full circuit thus gives priority to V_Ext. If Both V_Ext and VUSB are present, V_Ext is connected to +5V. If only VUSB is present and V_Ext is open, then Q5-2 will have zero volts at its gate, and R26 will be seeing an open circuit, opening the VUSB "switch", allowing VUSB to power +5V.

Notice first that there are two identical structures repeated, consisting each of two PMOS, a 10k resistor, and NMOS arranged in a sort of T shape. A positive voltage on the gate of the NMOS allows current through, pulling the two PMOS gates down and effectively opening a path through their drains. This is a voltage controlled switch implemented with MOSFETs, it allows current in either direction, so it is not itself backflow prevention as you say.

Imagine for a second that the bottom of R26 is unconnected. In this modified circuit, the presence of VUSB places the full 5 volts on the NMOS gate, opening the switch and allowing VUSB to power +5V.

If you ground that same end of R26, the NMOS gate voltage will drop almost to zero due to R26 being much smaller than R25, thus cutting off VUSB from +5V. This means you can use a low voltage at this point to "supersede" the 5 volts available from VUSB, which the full circuit indeed does.

V_Ext is connected to an identical gate circuit, whose NMOS also pulls this "supersede" signal from the previous structure low. The full circuit thus gives priority to V_Ext. If Both V_Ext and VUSB are present, V_Ext is connected to +5V. If only VUSB is present and V_Ext is open, then Q5-2 will have zero volts at its gate, and R26 will be seeing an open circuit, opening the VUSB "switch", allowing VUSB to power +5V.

Edit: This circuit does actually provide backflow prevention between +5V and VUSB, now that I simulate it.