Timeline for Crystal load capacitor value selection
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
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| Apr 26, 2023 at 7:49 | vote | accept | CommunityBot | ||
| Apr 24, 2023 at 12:04 | history | edited | Andy aka | CC BY-SA 4.0 |
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| Apr 24, 2023 at 11:48 | history | edited | Andy aka | CC BY-SA 4.0 |
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| Apr 24, 2023 at 11:16 | comment | added | Andy aka | If a device has dedicated pins for a XTAL then they won't be IO pins. I accept that an MCU that can use IO lines for driving a crystal will have more similar (and greater) input and output capacitance @Justme | |
| Apr 24, 2023 at 11:13 | comment | added | Justme | So I guess every datasheet and application note ever made to include the pin capacitance of chip internal IO pin structures for both input and output pins are wrong then. | |
| Apr 24, 2023 at 11:04 | comment | added | Andy aka | @Justme because the driver output (XTALOUT) and its very-necessary effective series resistance (needed for an accurate clock frequency) presents a very low effective capacitance. | |
| Apr 24, 2023 at 10:58 | comment | added | Justme | Why is the IC pin capacitance assumed to be on one pin but not on the other? | |
| Apr 24, 2023 at 10:56 | history | edited | Andy aka | CC BY-SA 4.0 |
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| Apr 24, 2023 at 10:29 | history | answered | Andy aka | CC BY-SA 4.0 |