Timeline for How do I create a 8-bit binary digit out of the combination two 7-bit ASCII values?
Current License: CC BY-SA 4.0
13 events
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| Jun 8 at 22:04 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| May 31, 2023 at 15:11 | comment | added | brhans | A naive implementation (assuming the inputs are always valid values) would be to simply ignore the upper nibble of each digit and then feed the lower nibbles into a BCD to binary conversion block (something like a reverse double-dabble, although I don't know if that can be done in 'simple' logic). | |
| May 31, 2023 at 12:34 | comment | added | periblepsis | @123Q Just in my head, no attempt at optimization, I count 27 2-input gates. That's 4 full adders (5 gates each), 3 half adders (1 XOR + 1 AND) and one XOR. And more gates can be removed. It's not optimized. My head can hold only so much. | |
| May 31, 2023 at 10:42 | answer | added | Simon B | timeline score: 1 | |
| May 31, 2023 at 8:37 | comment | added | greybeard | (Find previous Q&A) | |
| May 31, 2023 at 7:00 | comment | added | Marcus Müller | what does "this is digitally" mean? What is the technology you're relying on? "Efficiency" depends on the tool you might have at hand. | |
| May 31, 2023 at 6:50 | history | edited | 123Questions | CC BY-SA 4.0 |
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| May 31, 2023 at 5:33 | comment | added | 123Questions | So my implementation isn't less efficient than creating/using a multiplier circuit? | |
| May 31, 2023 at 5:22 | comment | added | greybeard | (All of the alternatives listed by The Photon are for digital circuits. In addition/as an alternative to tag logic-gates the is digital-logic. Have a look at SN74S484 datasheets to see how it was done with smallish lookup tables ((P)ROMs).) | |
| May 31, 2023 at 5:07 | comment | added | 123Questions | Oh, this is digitally. I'm not exactly sure how to add a digital logic tag | |
| May 31, 2023 at 4:37 | comment | added | The Photon | How do you plan to implement this physically? Discrete logic? CPLD? FPGA? | |
| May 31, 2023 at 4:37 | comment | added | greybeard | Basically, you are taking the ten's digit binary value, multiply it by 10 (b1010) and add to the ones digit bits. Bits 0 and 7 are trivial, "the middle bits" anything but. There are many ways to implement such, I think your 2+ level gate implementation looks good to go. For one implementation for multiple digits without a huge multiplier look at reverse double dabble. | |
| May 31, 2023 at 4:24 | history | asked | 123Questions | CC BY-SA 4.0 |