TL;DR: With two nMOSFETs in series, why does the load experience current spikes during switching times of one transistor even when the other is off - and how can I avoid it?

Consider the following circuit, simulated in LTspice:

Use case: It's a boiled-down version of an IR emitter driver I'm trying to design, which modulates a lower-frequency pulse train B on top of a higher-frequency carrier signal A, as in the Philips RC-6 remote control protocol. For the purposes of this question, unimportant details like the LED itself, gate pull-downs, etc. have been removed.

When I simulate the circuit and check the load current across R3, I see this:

When Q1 is off, the load still sees some current spikes (upper yellow circle) when Q2 switches - up to 3 mA, which is plenty to get some unintended light out of an LED. I understand that due to gate capacitance, there can be high current when switching the transistor (lower yellow circle). And I know I can limit this current by increasing the value of R1 and R2.

But what I don't understand is why these current spikes are transferred (directly or indirectly) to the load.

If I increase R1 and R2 to 10k, both the gate drive current and the spikes seen by the load are drastically reduced:

But consequently the switching is much slower, and the edges aren't as crisp. Is there another way to modify the circuit so that the transistors switch faster, but the load does not see current spikes during switching times of one transistor when the other is off?

To clarify: For this particular application, I'm sure increasing R1 and R2 is a workable solution, and at these frequencies, BJTs might be a better choice anyway. But this is a learning experience for me, and I'd like to understand this behavior. Thanks in advance!

TL;DR: With two nMOSFETs in series, why does the load experience current spikes during switching times of one transistor even when the other is off - and how can I avoid it?

Consider the following circuit, simulated in LTspice:

Use case: It's a boiled-down version of an IR emitter driver I'm trying to design, which modulates a lower-frequency pulse train B on top of a higher-frequency carrier signal A, as in the Philips RC-6 remote control protocol. For the purposes of this question, unimportant details like the LED itself, gate pull-downs, etc. have been removed.

When I simulate the circuit and check the load current across R3, I see this:

When Q1 is off, the load still sees some current spikes (upper yellow circle) when Q2 switches - up to 3 mA, which is plenty to get some unintended light out of an LED. I understand that due to gate capacitance, there can be high current when switching the transistor (lower yellow circle). And I know I can limit this current by increasing the value of R1 and R2.

But what I don't understand is why these current spikes are transferred (directly or indirectly) to the load. Why is this?

If I increase R1 and R2 to 10k, both the gate drive current and the spikes seen by the load are drastically reduced:

But consequently the switching is much slower, and the edges aren't as crisp. R3 also still sees current spikes up to 160 uA - much better, but not perfect.

Is there another way to modify the circuit, without limiting gate current, so that the load does not see current spikes during switching times of one transistor when the other is off?

To clarify: For this particular application, I'm sure increasing R1 and R2 is a workable solution, and at these frequencies, BJTs might be a better choice anyway. But this is a learning experience for me, and I'd like to understand this behavior. Thanks in advance!