Timeline for Ringing issue in DC load circuit simulation in LTSpice

Current License: CC BY-SA 4.0

7 events

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Sep 17, 2023 at 14:32	comment	added	Prashant		I feel like I'm learning more from just being on this forum then my entire 4 yrs of engineering. Thanks a lot for clear , crisp and real-world explaination for this problem.
Sep 17, 2023 at 14:07	comment	added	Spehro 'speff' Pefhany		To test this (including in simulation), you should use square waves which are much more likely to excite oscillation or ringing than sine waves.
Sep 17, 2023 at 14:06	comment	added	Spehro 'speff' Pefhany		@Prashant Capacitive loading (such as the gate in the MOSFET with only 1Ω in series effectively) can destabilize most op-amps. The series resistor makes it much worse (the op-amp itself has poorly documented ~100Ω output resistance). By adding significant phase-shift to the feedback you're (at a minimum) decreasing phase margin. The theory behind in-loop compensation such as I used is covered in this AD paper, but note that it's somewhat guesswork since the output resistance is not well known.
Sep 17, 2023 at 13:27	comment	added	Prashant		Also, may I ask the theory behind the capacitor and resistors (R2, R3 and C1) and how's it helping eliminate the ringing ? My understanding is that the three elements create a RC filter which elimitated the harmonics (ringing). Is my assumption correct ?
Sep 17, 2023 at 13:24	vote	accept	Prashant
Sep 17, 2023 at 13:23	comment	added	Prashant		Thanks for your response. It seems the 1nF capacitor and changing R3 to 680 ohms did the trick. I am now getting full current resolution without any ringing. Regarding the V3, I am only using sine wave to test the characterstics of variable DC input. In real world it will be 0 - 5VDC and thus my input reference will never go in negative.
Sep 17, 2023 at 8:10	history	answered	Spehro 'speff' Pefhany	CC BY-SA 4.0