Timeline for How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
Current License: CC BY-SA 4.0
13 events
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| Feb 15 at 23:13 | comment | added | EE18 | Crystal clear, thank you so much as always! @Neil_UK | |
| Feb 15 at 19:49 | comment | added | Neil_UK | @EE18 There are two ways two ways this can happen, voltage, and time. Say the output stays at 50% VCC for a while. This is precisely where different receiving gates can have different decision thresholds. It's why '1' and '0' have such a margin between them, CMOS only guaranteeing >70% and <30% respectively. It would be unremarkable for one gate to switch around 45% and another 55%. Then time. Say the metastable output resolves to a solid logic level, after another gate has read it in the other state. That way, even the same receiver can read it differently on two different clock cycles. | |
| Feb 15 at 18:42 | comment | added | EE18 | Hi Neil, hope all is well. Just returning to this here. Would it be possible to confirm with respect to your example why exactly two units might read the metastable latch output (i.e. the output in the "forbidden zone") differently. Both see the same (analog) voltage right? Are you just saying that it's possible for some reason or another that propagation of that input (analog) voltage could resolve to a 1 or 0 (HIGH or LOW voltage) in each unit? @Neil_UK | |
| Jan 15 at 16:08 | comment | added | EE18 | @Neil_UK Fantastic, thank you so much for that example. I've noted it away in my text here :) | |
| Jan 15 at 9:44 | comment | added | Neil_UK | @EE18 An example. The classic problem is an interrupt arriving at an MCU. Should the next instruction address come from the program counter, or the interrupt unit? If those two units read a interrupt latch output differently due to metastability, then neither, or both, might attempt to drive the address bus, resulting in a crash. This happened a lot to early PCs before it was 'fixed'. | |
| Jan 14 at 23:00 | vote | accept | EE18 | ||
| Jan 14 at 23:00 | comment | added | EE18 | Got it, thank you! | |
| Jan 14 at 18:05 | comment | added | jp314 | If you allow a metastable state to propagate (say by only using a single DFF), then if that signal drives (e.g. fan-out) to separate logic gates, then EACH of those may have a different interpretation of the logic level. This 'illogical' condition may not have been expected in the logic design and can cause erroneous behavior. | |
| Jan 14 at 15:01 | comment | added | EE18 | ... is exactly 1, whereas if we add FF2 (or FF3 etc. as you say) then that conditional probability (again given a metastable output of FF1) is, say, \$10^{-9}\$ (or better)? | |
| Jan 14 at 15:00 | comment | added | EE18 | ...potentially ruin the logical correctness of the outputs of this combinational circuit. But how is this any different than having FF2 which, we acknowledged, may or may not capture the intended logic level? That is, I'm still not sure I follow what the "problem" is (if not power) if whether we get an invalid logic level or a valid logic level, we may not have captured the intended logic level? 2) I think I perfectly understand your answer here but just want to confirm -- is the idea that if we only have FF1 then our probability of a metastable output given a metstable output of FF1... | |
| Jan 14 at 14:57 | comment | added | EE18 | Thank you for this very nice answer. Two quick follow ups before I accept: 1) I'm not sure I totally follow what you mean by "The main unwanted effect of metastability is that the perceived value (by a subsequent logic gate) may change between clock cycles which is not what is intended by using a DFF in the first place. " Would it be possible to give a quick example? That is, let's suppose we only use FF1 and it captures a metastable output state. Now the combinational circuit behind FF1 will see this invalid level at its (the combinational circuit's) inputs and you say that this will... | |
| Jan 14 at 8:42 | comment | added | Criticizing Israel not allowed | And cryptographers use 3 or 4 because they know it's good to have several orders of magnitude of safety margin :) 10^-18 events happen once per second somewhere in the world. | |
| Jan 14 at 1:48 | history | answered | jp314 | CC BY-SA 4.0 |