Timeline for Why can't you mix edge signals with level signals in SystemVerilog for synthesis?
Current License: CC BY-SA 4.0
8 events
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| Feb 8 at 17:44 | comment | added | toolic | @EE18: Yes, that is my understanding of it. | |
| Feb 8 at 17:40 | history | edited | toolic | CC BY-SA 4.0 |
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| Feb 8 at 17:40 | comment | added | EE18 | I see I think. So you're saying it's not an in principle objection to the particular snippet I wrote (i.e. you could write a compiler that would also synthesize correctly with this) but rather that we make an in practice decision to simplify and only allow certain constructs as synthesizable? | |
| Feb 8 at 17:38 | comment | added | toolic | @EE18: It's hard in the sense that there are too many ways to write Verilog code to do the same thing in simulation. See my updated answer. | |
| Feb 8 at 17:36 | history | edited | toolic | CC BY-SA 4.0 |
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| Feb 8 at 17:29 | history | edited | toolic | CC BY-SA 4.0 |
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| Feb 8 at 17:29 | comment | added | EE18 | I see. I guess my question is about why this particular construct would be so hard to infer, but I guess I'd need to know a lot more about hardware language compilation in order to answer that? | |
| Feb 8 at 17:28 | history | answered | toolic | CC BY-SA 4.0 |