Timeline for Why does this vintage DRAM chip enable circuit require such a beefy resistor?
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
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| May 8 at 23:21 | comment | added | Kuba hasn't forgotten Monica | @BZo It's a double whammy. High resistance not only prolongs the RC delay, but it also prolongs the switching time of the saturated transistor. Q1 is saturated, and the higher the collector current, the faster it will switch off as the base charge bleeds at a rate proportional roughly to collector current. | |
| May 8 at 2:26 | history | edited | TimWescott | CC BY-SA 4.0 |
Clarify why the multiply by 8
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| May 7 at 23:57 | comment | added | BZo | @kruemi Hmmm thank you. More to learn on RC time vs rise time. Thanks for the heads-up! | |
| May 7 at 7:06 | comment | added | kruemi | @BZo in a simple RC you get to about 63% of U0 within 1 Tau. Time constant is not the same as rise time (I've fallen for this in the past too :)). And it's not only about the rise time but about clock and access times too. If the Processor issues the CE signal it expects the RAM to be ready within a certain time.... | |
| May 6 at 20:46 | comment | added | Russell Borogove | Multiply by 8 for the 8 chips sharing the CE? | |
| May 6 at 6:02 | vote | accept | BZo | ||
| May 6 at 5:22 | comment | added | BZo | Ah, thank you. So to be sure I'm understanding, the thing that is in tension/tradeoff here is the rise time of the CE signal-- make the pull-up resistor 1k and you'll save a lot of power but the timing of the signal won't be suitable anymore, right? Datasheet (linked in the question) says 27pF max at chip enable, *8 = 216. Assuming no extra margin for clarity here and 130ohms, that's ~28ns time constant, well within the 40ns rise time requirements in the datasheet. But if you make that resistor 1k, it could be 1/4W but your rise time is now 200ns, unacceptable. Sound right? Thanks! | |
| May 6 at 4:56 | history | answered | TimWescott | CC BY-SA 4.0 |