Timeline for Confused about layout guidelines for TPS63710 buck converter
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
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| Jul 8 at 19:58 | vote | accept | AJ-D2 | ||
| Jul 7 at 8:22 | comment | added | Justme | @TimWilliams That is a good question. Often manufacturers suggest you an example layout, and they are just that, suggestions. There may be better or worse layouts and it will affect the performance of the chip or emitted interference or output ripple or whatever - and even a poor layout could do just fine in your application. However, if a manufacturer tells you to specifically put a capacitor weirdly between two pins directly, they have a good reason to say that, and when asked, they will some reason, but in reality, it may just be a workaround for a silicon bug. | |
| Jul 7 at 0:47 | comment | added | Tim Williams | Interesting, do you have measurements of these pins (peak currents, rate, susceptibility)? You say it's important, but how much really matters, what trace width and length will have what kind of effect? | |
| Jul 7 at 0:19 | history | edited | Justme | CC BY-SA 4.0 |
added 250 characters in body
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| Jul 7 at 0:13 | history | answered | Justme | CC BY-SA 4.0 |