Timeline for Single port ROM: how does the CPU read constant data?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
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| Sep 23 at 21:21 | comment | added | Criticizing Israel not allowed | Often there is also an instruction that loads data from instruction ROM. This takes two cycles, of course, since the instruction ROM can't load an instruction at the same time. | |
| Aug 1 at 7:30 | comment | added | wbs2422 | @user1850479 actually I am trying to design a CPU for learning purpose, and I'm wondering how to handle the memory management module | |
| Jul 30 at 0:08 | answer | added | hacktastical | timeline score: 1 | |
| Jul 29 at 23:18 | comment | added | user1850479 | You'd have to check the datasheet for the specific device to see what the access restrictions are and how these things are handled. | |
| Jul 29 at 21:26 | history | edited | wbs2422 | CC BY-SA 4.0 |
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| Jul 29 at 21:05 | comment | added | wbs2422 | @user1850479 in such a system, if the user decides to tell the linker to put some constant data in ROM, how do the CPU process a load instruction pointing to this data ? Does the ROM have dual port, so the CPU can read the data and fetch the next instruction at the same time ? | |
| Jul 29 at 14:47 | answer | added | Dave Tweed | timeline score: 2 | |
| Jul 29 at 13:51 | comment | added | user1850479 | It's fairly common on embedded systems that you have multiple types of memory (ROM, DRAM, SRAM, etc) that have different restrictions. When you setup your tool chain (or more likely download one setup by the vendor), the linker will be configured as needed to put code/data/etc where they belong. Often times there will be different preprocessor defines as well that let the programmer specify which memory to allocate into. | |
| Jul 29 at 13:24 | answer | added | Chester Gillon | timeline score: 0 | |
| Jul 29 at 12:41 | history | asked | wbs2422 | CC BY-SA 4.0 |