I have a negation operation and two types of "logic gates" with following outputs (A, B are inputs):
"gate" 1:
A | B | OUT
x 0 1
0 x 1
0 0 1
0 1 x (no output)
1 0 x (no output)
x x x (no output)
1 1 0
x 1 0
1 x 0
"gate" 2:
A | B | OUT
x 0 0
0 x 1
0 0 x (no output)
0 1 1
1 0 0
1 1 x (no output)
x 1 1
1 x 0
x x x (no output)
I can join these two "gates" to form the third one:
A | B | OUT
x 0 x (no output)
0 x 1
0 0 1
0 1 1
1 0 0
1 1 0
x 1 x (no output)
1 x 0
x x x (no output)
Is it possible to use these (half gates or joined gates) to build regular binary logic NOR or NAND gates, given that it is possible to additionally negate any input and/or output?.
Negation op is:
A | OUT
x x (no output)
0 1
1 0
The problem
The main difficulty is to make the "joined gate" inputs (0,1) and (1,0):
A | B | OUT
0 1 1
1 0 0
to always output 1 or 0 like:
A | B | OUT
0 1 0
1 0 0
This is the only change needed to get the NOR gate. The question is how to do it with these "gates", if it's possible at all.