Timeline for RISC-V Exercise: why is `MemtoReg = 1`?
Current License: CC BY-SA 4.0
6 events
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| Oct 25 at 11:31 | comment | added | periblepsis |
True. But why does that matter? This is all about instruction decoding that takes placed in the control unit at the IF/ID latch and following logic. This is then pushed forward until it is needed in the WB stage. Either way, whether decoded one way or else the other way, the only important matter is that the control unit set things up so that RegWrite would be 0 when the time came. I just don't understand why you care so much about this. So long as RegWrite=0 the value of MemToReg is x (don't care.) Either value has the exact same effect -- none at all.
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| Oct 25 at 10:49 | comment | added | Sam | @periblepsis because the output of the MUX will be different. | |
| Oct 25 at 5:41 | comment | added | periblepsis |
Given that RegWrite=0, why does it matter to you whether MemToReg is 1 or 0?
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| Oct 24 at 23:34 | comment | added | Sam | @periblepsis Well, that does mean that nothing will get written into the register. However, what I'm trying to figure out is the output of the MUX. | |
| Oct 24 at 22:32 | comment | added | periblepsis |
RegWrite will be 0. So no worries.
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| Oct 24 at 21:46 | history | asked | Sam | CC BY-SA 4.0 |