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Accessing RAM instance from differentmultiple modules in Verilog

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Accessing RAM instance from different modules in Verilog

I am trying to make a single instance of RAM module accessible in different modules without instantiating it in every module. Since If I instantiate RAM module in each module, there are two more copies of it, taking up twice or more as much Block RAM as needed. There is no concern about modules trying to access it in the same time, as they run one after the other. How can I do it?

P.S. providing memory as input to each module seems like incorrect solution..