Timeline for Shared parameter for several modules (Verilog)
Current License: CC BY-SA 3.0
3 events
| when toggle format | what | by | license | comment | |
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| Aug 29, 2013 at 10:07 | comment | added | shuckc |
I prefer to have top level blocks pass parameters down to children explicitly as @dave_tweed suggests, rather than `include files. Preprocessor based solutions sometimes give problems with tool/simulator flows later.
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| Aug 20, 2013 at 9:23 | vote | accept | YAKOVM | ||
| Aug 20, 2013 at 0:21 | history | answered | Dave Tweed | CC BY-SA 3.0 |