Timeline for Custom FPGA PCB with external programming circuit
Current License: CC BY-SA 3.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 13, 2014 at 12:19 | comment | added | shuckc | How quickly (ms?) do you require the device to be functioning out of power-up reset? There are trade offs to be made: parts are cheaper for SPI configuration but takes a couple of seconds to come up. Altera's CPLD based parallel programming is quicker to DONE state out of reset. | |
| Dec 3, 2013 at 17:54 | vote | accept | technocratic | ||
| Nov 30, 2013 at 11:23 | comment | added | FarhadA | Well, you can get a USB blaster copy from many sources for as low as $10. Most of them are pretty fast and work really good. | |
| Nov 29, 2013 at 11:39 | answer | added | Martin Thompson | timeline score: 2 | |
| Nov 28, 2013 at 20:57 | answer | added | alex.forencich | timeline score: 1 | |
| Nov 28, 2013 at 11:56 | answer | added | HeyYO | timeline score: 2 | |
| Nov 27, 2013 at 21:15 | answer | added | Dave Tweed | timeline score: 4 | |
| Nov 27, 2013 at 21:14 | review | First posts | |||
| Nov 27, 2013 at 22:51 | |||||
| Nov 27, 2013 at 20:59 | history | asked | technocratic | CC BY-SA 3.0 |