Understand a counter in VHDL

Question

I'm trying to understand the description of a counter in VHDL:

entity counter is port ( 
    load, reset, clk: in bit; 
    input: in integer range 0 to 255; 
    output: out integer range 0 to 255);
end counter;

architecture behaviour of counter is 
begin
   ctr: process
      variable value: integer range 0 to 256 := 0;
      begin
         --update value
         if(clk'event) and (clk= '1') then 
            value := value + 1;
         elsif load= '1' then value := input; 
         elsif reset = '1' then value := 0;
         end if;
               
         if value = 256 then value:= 0; end if;
         
         --output value
         output <= value;
         
         --wait on changes in input signals
         wait on clk, load, reset;
   end process;
end behaviour;

but I don't really get it. There are a lot of examples of counters out there but each is one is completely different from the other and meanwhile, I don't know where to get answers. This entity will be used along with this testcounter:

entity testcounter is end testcounter;

architecture behaviour of testcounter is 

   component counter port( 
      load, reset, clk: in bit; 
      input: in integer range 0 to 255; 
      output: out integer range 0 to 255
   );
   end component;

   signal load, reset, clk: bit;
   signal input: integer range 0 to 255; 
   signal output: integer range 0 to 255;
   begin DUT: counter port map(load, reset, clk, input, output);
   
   --Simulation.
   process
   begin
      --Simulation: Load.
      for c in 0 to 255 loop
         input <= c;
         wait for 25 ns;
         load <= '1';
         wait for 50 ns;
         load <= '0';
         wait for 25 ns;
         assert input= output report "Load: output wrong";
      end loop;
      
      --Simulation: Reset.
      reset <= '1';
      wait for 50 ns;      
      reset <= '0';
      wait for 25 ns;
      assert output = 0 report "Reset: output wrong";
      
      --Simulation: Count. 
      for c in 0 to 255 loop
         assert c = output report "Count: output wrong";      
         clk <= '0';
         wait for 25 ns;
         clk <= '1';
         wait for 50 ns;
         clk <= '0';
         wait for 25 ns;
      end loop;
      assert output = 0 report "Count: overflow wrong";
      
      --Simulation: Reset.
      reset <= '1';
      wait for 50 ns;      
      reset <= '0';
      assert output = 0 report "Reset: output wrong";
      
      wait;
  end process;
end behaviour;

but I'm fine if I could get help understanding the counter. I have seen several descriptions and I think I know how counters work conceptually but lack the knowledge how to implement them. I understand programming itself but I don't get the meaning of the clock, load and reset and their results when the one is zero or one. Could somebody explain? I'm also glad if you could point me to proper sources where I can look that up!

added gtkwave:

Answer 1

The first and probably most important thing with VHDL is to understand that it's not a programming language but a hardware description language. You're not writing sequential code blocks but rather describe logical and combinatorial hardware.

It depends a little how deep you wanna dive into this topic, but you could read something about counter implementation using logic gates.

What your counter does is it evaluates the value of value with every rising edge of the incoming clock. This is another speciality of VHDL, where in sequential programming language the clock is something you don't really see, it's a crucial part of every VHDL design.

Regarding your example, as already stated by Brian Drummond, that's not really proper code. Your process needs a sensitivity list to be simulated. A sensitivity list tells the simulator what signals it has to watch for re-evaluating the process. In your case this would be clk, load and reset.