Reading the Boolean Expression for a Logic NAND Gate

Question

From https://www.electronics-tutorials.ws/logic/logic_5.html

I learned that Boolean Expression for a 3-input Logic NAND Gate is

, and is read as "A AND B AND C gives NOT Q".

I am wondering why it's not read as "NOT (A AND B AND C) gives Q" as this seems to me aligns with the Boolean Expression more.

Answer 1

Exciting, what a day! That is the most precise statement. I got the answer from the. posted link!

"Read as" => Read the Symbol from the left to the right: [A & B & C] [gives (the container/function with '&' operation)] [NOT (the hollow dot)] [Q] !!

1. "NOT (A AND B AND C) gives Q" can be perceived as "Not (A & B & C) but something else may give Q", and that isn't a binary opinion.
   
2. Considering the nuance of 1) feels something off, "A AND B AND C gives NOT Q" sounds like "(A & B & C) gives something (and that is) NOT Q". Better!
   

Answer 2

It is usually read as your suggestion. But there's no contradiction, both statements mean the same. Why the authors of the site you're referring to chose their way of expressing it - no idea.

Answer 3

Boolean logic's overbar notation isn't very friendly to text editors. The electronics-tutorials.ws folks seem to struggle a bit with this.

Here at SE, we can deal. The expression, formally, would be:

$$ Q = \overline{ABC} $$

Anyway, I used an SE syntax called mathjax to show this fancy overbar stuff, which codes as follows:

$$
Q = \overline{ABC}
$$

More about this here: Most common MathJax uses in Electrical Engineering?

Now, if you were to code this as a C language expression (C being a language that doesn't know anything about overbars) you'd get:

 Q = !(A && B && C);

They're nevertheless the same expression. As there are so many people who use C, you'll see this form often as it's easier to represent with normal text. Verilog borrows from C and uses this form as well. VHDL? Enjoy your verbose typing...

Anyway, all these forms read as "NOT (A AND B AND C) gives Q", as you said.

Now, to say "(A AND B AND C) gives NOT Q" is a bit confusing, but it's still valid, kind of. Nevertheless, C language and Verilog will not allow a unary NOT operator on the left-hand side of an expression.

That is, this format isn't allowed:

  !Q = A && B && C;    // "(A AND B AND C) gives NOT Q" - nope

While this format is a-ok:

   Q = !(A && B && C);  // "NOT (A AND B AND C) gives Q" - ok

Bottom line: your reading as "NOT (A AND B AND C) gives Q" is preferred to the one given on that website.