Impedance matching in 2-layer FR4 board

Question

I'm not that familiar with high-speed boards designing. Here I want to route the PCB in a part of which I've used a LAN8720A as the PHY of the ethernet system. According to what I've read about ethernet, the single-ended impedance should be 50 Ω. I've designed my Layer Stack Manager in Altium Designer as below:

To be honest, the results surprised me because the suggested trace width is about 120 mil, which does not seem to be normal. Did I make some mistakes in settings? Or is the 2-layer FR4 material not appropriate?

---

I saw this question which has the schematic below, using 10 Ω resistors for series termination.

Are these resistors for impedance matching ? Could I use something like that?

Answer 1

No the calculation looks okay, the problem is with the two layer board the reference plane is 60 mils or more from the trace. You can think of it like this: Transmission lines need a certain width to height ratio, if the height is increased you must also increase the width.

So you either need to decrease the height, or increase the dielectric constant of the transmission line to get a smaller width. Seeing as how four layer boards are so cheap these days it might be worth just going to a four-layer board, then a non-standard stack up but you'd have to consult with your PCB manufacturer.

Another thing is it might be difficult to maintain low inductance digital pathways with the two layer board for the MII or RMII interface (especially the 50 MHz for RMII)

are these resistors for impedance matching goal? may I use something like this?

Those resistors are pull ups for the transceivers on the LAN8720A. One thing you might try if you really need a 2 layer board is keeping the traces very very short between phy and magnetics (and between magnetics and connector).

Answer 2

For two layer boards, a coplanar waveguide geometry usually gives more useful dimensions than a microstrip geometry. A coplanar waveguide with groundplane distance H = 1.5 mm, trace width W = 0.4 mm, trace spacing S = 0.1 mm gives roughly 50 ohms impedance. For differential pairs, a coupled microstrip line can work also.

But also consider the speed of the signals you are routing and the length of the traces. The 10 ohm series resistors slow down the rise and fall time of the signal, reducing the effect of any impedance mismatches. A common rule of thumb is that impedance matching is not needed if the trace length is less than quarter of the electrical length of the rise time.

It is often hard to find exact specifications for the rise and fall times of digital signals, as it depends on the capacitive load and output impedance of the pin. With the 20 ns period of the RMII interface clock, the rise times could be several nanoseconds without disturbing the bus function. This in turn would give a limit of about 10 cm before needing impedance matching. The series resistors provide an easy way to adjust the rise time based on measuring a prototype.

Answer 3

That is an expected result. Not the numbers but as a concept of using standard 1.6 millimeter thick board for this.

It is too thick to have sensible 100 ohm differential traces over a ground plane.

Answer 4

As others have mentioned, for a 50 Ohm microstrip, 62 thou above a plane, a 120 thou trace for FR4 is about right. As a second opinion, here is what Saturn PCB toolkit says:

If a 120 thou trace is too wide, moving the plane closer to the trace will help. This can be done by using a thinner board, or going to four layers (signal / plane / plane signal).