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I am implementing a circuit that takes two ASCII values that are in the range 0x30 - 0x39[0 - 9] for the tens digit and ones digit, and then combine them, and output a proper 8-bit binary value reflecting this. D1 is the ten's place digit, D0 is the one's place digit

For example: D1 = 0x311, D0 = 0x32[2]. This means the number is 12, so the output would be 00001100. I have been able to implement this by taking D1 and D0, turning those into binary values, and then using complicated logic to combine them into the respective number. So the output can be any value 0 - 99.

It takes a staggeringly large amount of gates. See below. At this point I'm wondering if it is more efficient to just directly compare the ASCII values and use a chain of AND gates(also inefficient). Does anyone have advice for doing this more efficiently? Also, I don't want to use any components that are analog in some way.

this is goofy

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    \$\begingroup\$ Basically, you are taking the ten's digit binary value, multiply it by 10 (b1010) and add to the ones digit bits. Bits 0 and 7 are trivial, "the middle bits" anything but. There are many ways to implement such, I think your 2+ level gate implementation looks good to go. For one implementation for multiple digits without a huge multiplier look at reverse double dabble. \$\endgroup\$
    – greybeard
    Commented May 31, 2023 at 4:37
  • \$\begingroup\$ How do you plan to implement this physically? Discrete logic? CPLD? FPGA? \$\endgroup\$
    – The Photon
    Commented May 31, 2023 at 4:37
  • \$\begingroup\$ Oh, this is digitally. I'm not exactly sure how to add a digital logic tag \$\endgroup\$
    – 123Questions
    Commented May 31, 2023 at 5:07
  • \$\begingroup\$ (All of the alternatives listed by The Photon are for digital circuits. In addition/as an alternative to tag logic-gates the is digital-logic. Have a look at SN74S484 datasheets to see how it was done with smallish lookup tables ((P)ROMs).) \$\endgroup\$
    – greybeard
    Commented May 31, 2023 at 5:22
  • \$\begingroup\$ So my implementation isn't less efficient than creating/using a multiplier circuit? \$\endgroup\$
    – 123Questions
    Commented May 31, 2023 at 5:33

1 Answer 1

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One solution would be an off-the-shelf ROM chip. But it does require you to obtain a suitable ROM programmer.

If you are certain that the inputs are always valid ASCII digits, then you only need the least significant 4 bits of each. So a 256 byte ROM (8 address lines, 8 data lines) would do.

If you want error checking, a 64k byte ROM (16 address lines, 8 data lines) would allow you to output an error code (a number over 100) if the inputs are invalid.

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  • \$\begingroup\$ For the error checking, the logic on the upper nibbles can be mostly independent of the logic on the lower nibbles. Two 256-byte ROMs and some glue logic might be more cost-efficient than a single 64 kB ROM. \$\endgroup\$
    – The Photon
    Commented May 31, 2023 at 15:15
  • \$\begingroup\$ The LSB can just be passed through, leaving 2×7-1=13 address bits. As just 6 more bits are needed for numbers up to 99, 8K×6 bits would do, if necessitating a 3-input AND/NAND to detect an error code. A parallel output ROM would likely offer a tri-state output, ×8 enough for binary and decoded error signal. \$\endgroup\$
    – greybeard
    Commented Jun 1, 2023 at 11:11

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