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In many of the PCBs of my company we have done the stack-up as following:

(stack-up A)

  1. Pads/GND/Some LF signals
  2. Signal1
  3. Signal2
  4. GND plane
  5. PWR planes (more than one due to several secondary supplies needed)
  6. Signal3
  7. Signal4
  8. Pads/GND/Some LF signals

However on a new design of ours I am revisiting the issue, as I believe the stack-up is not ideal. I see problems at the adjacent layers (I guess this will work without cross-talking only if the signals are perpendicular) and at the fact that it is difficult to make impedance controlled lines at the internal layers 2,3,6 and 7). Also I am not sure if it the best solution regarding the return path currents.

Am I true? What do you believe?

On the other side I have to say that the boards until now didn`t have obvious serious problems of EMC, signal integrity etc.

What other stack-up would you recommend? I am thinking either this:

(stack-up B)

  1. Pads/GND/Some LF signals
  2. Signal1
  3. GND plane
  4. Signal2
  5. Signal3
  6. PWR planes
  7. Signal4
  8. Pads/GND/Some LF signals

or

(stack-up C)

  1. Pads/Signal1
  2. GND plane
  3. Signal2
  4. GND plane
  5. PWR planes
  6. Signal3
  7. GND plane
  8. Pads/Signal4

My concern at Stack-up C is that I will not have shielding on the outer layers. Could I solve this by filling the gaps in Layer1 with GND?

Also at Stack-up B what will be the reference plane for the return path currents for Signal1 (and Signal4)? Will it be Layer3 (Layer6) as intended or Layer1 (Layer8)? Does it depend on which layer is closer to the signal layer?

What is your opinion?

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    \$\begingroup\$ This depends completely on what you're doing. Are you running PCI Express? That gets kinda touchy about route impedance! C might be a better option. Do you need more space on the outside surfaces for parts? B might be a better option. \$\endgroup\$
    – Daniel
    Commented Jul 10, 2016 at 20:34
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    \$\begingroup\$ How many signal routing layers do you actually need? Is 2 for LF and 2 for HF enough, or do you really need 4 HF routing layers? \$\endgroup\$
    – ThreePhaseEel
    Commented Jul 10, 2016 at 20:37
  • \$\begingroup\$ To add to the other two comments: It might really be worth considering how many components you have on either side of the board; your 8th layer always being a Signal layer indicates your board has components on both sides, but maybe the bottom side is mainly used for passives/decoupling, so it might be the case that Signal3 or Signal4 could be omitted \$\endgroup\$
    – Marcus Müller
    Commented Jul 10, 2016 at 21:07
  • \$\begingroup\$ Can you consider a 10 layer PCB? sig - gnd - sig - sig - gnd - pwr - sig - sig - gnd - sig \$\endgroup\$
    – Claudio Avi Chami
    Commented Jul 10, 2016 at 21:14
  • \$\begingroup\$ putting PWR next to GND gets you a distributed capacitance that can help decouple your power supplies, try not to have the thick fiberglass layer between them. \$\endgroup\$
    – Jasen Слава Україні
    Commented Jul 11, 2016 at 1:37

1 Answer 1

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To me, option C provides no advantage over a 6-layer stackup. So it seems like a waste of money. Option C might make sense if you included two or more POWER planes (and if those power planes were actually needed). So I am inclined to rule out option C.

I don't care for option A, because it will be difficult to get desirable results for the breakout traces on top and bottom. Either the breakout traces will be excessively wide, or the impedance will be quite high compared to signal 2 and signal 3. But it could work OK if trace impedance is not a significant concern.

So of all your choices, I guess I like option B the best. It has the same problem as A, but the magnitude of the problem should be less.

But I would also urge you to consider using 6 or 10 layers (unless the board is not really sensitive to impedance issues).

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  • \$\begingroup\$ Well, that's the point. I don't know how sensitive it is to impedance issues. As I said, we have always used this stack-up to a lot of our old PCBs. And they still had SGMII, SSSMII interfaces and clock distribution lines. Now I also have a PCIe interface. Could you explain a bit what you mean with your second paragraph? I didn't get this about the breakout traces and what does that have to do with Signal 2 and 3. Why do you say B might have the same Problems with A? In what sense?Also this regarding the power planes? I indeed have and need more than one Power planes. Why C is better? \$\endgroup\$
    – nickagian
    Commented Jul 11, 2016 at 8:27
  • \$\begingroup\$ Well, the breakout traces, if these are SMT components (which is what I am assuming), will be on the top or bottom layer. Impedance is controlled by distance to the plane and trace width. Wider trace is lower impedance, and closer to the plane is lower impedance. So, looking at option B if a 5 mil trace on layer 2 is 50 Ohms, then a 5 mil trace on layer 1 will be more than 50 Ohms. Looking at option A, if a 5 mil trace is 50 Ohms on layer 3, then it will be greater on layer 2, and greater still on layer 1. \$\endgroup\$
    – user57037
    Commented Jul 11, 2016 at 8:37

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