Tuning a potential sensor using a source-follower MOSFET

Question

I am interested in building a simple but sensitive setup that would allow me to detect small potential changes (adsorption of ions) on the surface of the gate of a MOSFET - what is commonly referred to as an extended gate FET.

As a reference, see for example this figure from a research article (Song et al, Phys Rev E, 2006):

The idea is to shift Vth and detect that change because Vgs remains identical.

The extension of the gate is in contact with a solution containing the analytes, and the bias is provided at a reference electrode in the same solution.

From what I have understood, a common drain amplifier seems to be the best option to have a straightforward relationship between Vg and the measured Vs. A large resistance (R) is used to maximize the voltage drop across R. Stop me if anything makes no sense here.

I am unsure as to how to choose the MOSFET and the various parameters for maximal sensitivity and dynamic range. Importantly I want to use an "almost low-cost" equipment so I cannot observe current changes (usually very small) but rather changes in voltage at the source. Let's assume for the sake of this question that I have a good ADC.

My questions are therefore:

• How to rationalize the choice of the hardware? For example, would it make any difference to use a depletion or an enhancement mode MOSFET (except for the fact that the signal would go up vs down, which I don't really care about as long as it changes)?

• How to set Vd and Vg to make sure that changes are detectable? Initially I thought I would set Vd to a small value (but not too small, to preserve a decent dynamic range, my ADC operating in the 0-2.5V range it would be great to use the whole range) and then choose a somewhat arbitrary gate voltage above Vth, so that any change in Vgs would cause a change in Id, and therefore a change in Vds; as the drain potential is imposed, I would read a difference in potential at the source. But I also guess there must be some "ideal" set of conditions for that, which I cannot figure out. For example, should I operate in the saturation or the triode/linear mode?

• Which brings me to the big general question: How can I know a priori in which region I'm operating and what my device's characteristic voltages are, since I expect the source potential to be variable, and therefore Vds and Vgs to change in potentially unexpected directions?

Thank you for any advice or comments on this question!

Answer 1

Your graph would seem to show a p-enhancement fet.(Vgs is -ve for increasing IDD)

Perhaps the polarity of the gate has some effect in attracting/repelling the ions from the active gate selective coating area.

Yes the fet will be in saturation, i.e. operating as a constant current source.

I would expect that you would have a pair of matched fets on the die, with one exposed to ions and the other shielded from them. By doing that you get first order thermal compensation.

An actual IC circuit probably looks like an opamp input stage, and quite different to how you would do it outside of an IC.

This is a pfet version. Pay attention to the polarities. The opamp creates a "virtual earth" i.e. it always hold the source/-ve input at 0V. So VGS is not affected by the current

^{simulate this circuit – Schematic created using CircuitLab}