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I have the following circuit built up in LTSpice which will be used to switch in different sense resistors for current measurements.

Branches Switch Mechanism

The mAEn signal switches the M1 transistor on at t=10ms which allow current to flow through the 30m Ohm resistor in branch 2. M3 in branch 1 is turned off the entire time.

Here is a plot of the voltage on Vdev.

Output 1

The dip goes below 3.2V for about 10ns.

Now, if I remove Branch 1 like so.

Circuit 2

I simulate this circuit, there is no voltage dip on the Vdev net as can be seen below.

Output 2

Just cutting the line on the branch 1 path gives the same result (ie the following circuit also produces the same voltage as above with no dropout).

Circuit 3

Why is it that turning on the transistor with less line impedance (branch 2) the voltage drops. This is like having a pipe with a small amount of water flowing, then opening a valve to another pipe with much higher water pressure and the pressure in the original water pipe dropping when you do it? Can somebody explain what is going on here?

What modifications can be made to the circuit to remove the transient voltage drop but have multiple branches?

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  • \$\begingroup\$ It's possible that it's just a simulation singularity/bug. I have done a lot of SPICE modelling and simulations and they are quite frustrating indeed. What happens if you put a simple 10uF capacitor from VDev to ground? \$\endgroup\$
    – KyranF
    Mar 30, 2014 at 2:30
  • \$\begingroup\$ I will convert my comment to an answer, if you would be so nice as to vote it as answer.. I'm glad i could help. \$\endgroup\$
    – KyranF
    Apr 3, 2014 at 0:55

3 Answers 3

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It's possible that it's just a simulation singularity/bug. I have done a lot of SPICE modelling and simulations and they are quite frustrating indeed. What happens if you put a simple 10uF capacitor from VDev to ground?

the original poster followed this, and fixed their issue.

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Due to parasitic capacitance within the MOSFET (from gate to drain), when you drive the gate low (in order to turn it on), this transient is coupled through to the output and you see a short spike as per your simulation. I'd say this should be expected. If you want to get rid of (or reduce) this effect try slowing down the activation signal mAEn or uAEn.

Also, as a footnote, don't expect this type of circuit to work well when there is a high frequency AC superimposed on the DC because the MOSFET's parasitic drain-source capacitance will conduct some current when the MOSFET is supposedly inactive.

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As Andy mentioned it is the gate capacitance that affects the simulation. For simulation purposes you could add a resistor of 1k between the gate of M2 and R3.

Or a cleaner approach, modifiy your mAEn to look something like this: PULSE(0 3.3 10m 1m). (Initial 0V, Final 3.3V, rise at 10m seconds, risetime 1m second)

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