Primary and secondary currents of a transformer driven with clock pulse

Question

What will be the primary and secondary current waveforms of a transformer whose input is a clock signal?

I have set up a circuit using CircuitLab.

^{simulate this circuit – Schematic created using CircuitLab}

I used L_m to model the magnetizing inductance (i.e.; the inductance seen from the primary side when secondary is open). I don't know the best way of modeling it, so I tried both connecting it in series and parallel. When I omit it, the transformer behaves like ideal and perfectly conducts the pulse applied from primary side to the secondary side.

(L_m is in series with the primary.)

(L_m is parallel with the primary.)

These simulation results partly answers my question, but I also want to know what would happen when the duty cycle (D) varies between 0.1 to 0.9. How it looks like when there is a DC bias because of high duty cycle rates. And why the current waveforms are drawn as triangular wave (with straight lines) in theory. If connecting L_m in series is the correct way of modeling it, why the secondary side current is always at negative in this case.

Answer 1

Magnetizing inductance is in parallel with the perfect transformer model, not in series. Series inductance represents leakage inductance ie inductance that does not contribute to the magnetic field applied to the secondary winding..

Maybe you should try modelling both for a decent representation of reality. Then add on copper losses as series resistors and eddy current losses as a resistor in parallel with the primary. You should also consider self resonances due to interwinding capacitance.

Only then will you get a fair representation of reality.

Ignoring all the little effects of adding series and parallel resistance, inductance and capacitance, when you have 50:50 square wave going through a transformer you can forget about the DC content; the output will have an average value that is zero so, if the mark-space ratio were 10%, the output waveform would peak at 90% for 10% of the time and remain at -10% for 90% of the time.

If you need this to be tied to 0V so that at any reasonable MS ratio, the output voltage was clamped to round about 0V you'll need a series capacitor and a diode clamp to 0V. Now for a broad range of MS ratios, the peak voltage will be Vpk-Vdiode and the low voltage will be -Vdiode. Hope this helps.