As far as I know, the planar process of making IC, especially CMOS IC, is already a 3D process because a layer is added on top of an existing layer to realize various things (cf. Wikipedia IC Layout). So, in my opinion, an IC is already 3D because there are multiple interconnected vertical layers. Why people coined the terms 3D IC then? What does the planar process IC lack in the three dimensionality that 3D IC fulfills?
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There's a single surface of semiconductor, so doesn't matter how many conductor layers you have, you need to go down to ground level at every conductor terminal. Note, not the conductors is the heart of circuit, but silicon devices on surface of a chip. You cannot stack transistors one above another with current technology. This very limits IC grow to third dimension. So it's still 2D.
To be 3D, IC technology needs method to make and interconnect devices in bulk of semiconductor or method to make lots of stacked semiconductor films.
