Alright folks,
I've recently begun working through the design of an 8086 single-board in my free time to play with (for lack of a better word, I need to experience the rush of being close to low-level hardware again).
I had the intention of using 35ns-capable MRAM as a storage medium (program code/RAM) mainly as an experiment, but also because I have some devices laying around unsoldered. I've checked the datasheets and the device (MR2A16A) carries SRAM-compatible timing - it doesn't specify a max on its access timings, so initial thoughts are to give it a try.
The issue is that according to the datasheet, the 8086 uses the READY line as a signal to remove its bus (AD15-AD0) from the high-impedance state and read in the data (or at least, that's what I'm given to believe). Below is the section detailed "System Timing - Minimum Mode". It can be found here on page 12:
The read cycle begins in T1 with the assertion of the Address Latch Enable (ALE) signal. The trailing (low-going) edge of this signal is used to latch the address information, which is valid on the local bus at this time, into the address latch. The BHE# and A0 address the low, high, or both bytes. From T1 to T4 the M/IO# signal indicates a memory or I/O operation. At T2 the address is removed from the local bus and the bus goes to a high-impedance state. The read control signal is also asserted at T2. The read (RD#) signal causes the addressed device to enable its data bus drivers to the local bus. Some time later valid data will be available on the bus and the addressed device will drive the READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again 3-state its bus drivers. If a transceiver is required to buffer the 8086 local bus, signals DT/R# and DEN# are provided by the 8086.
Obviously, no memory controller nowadays is going to rely on a discrete signal that tells it when data has appeared. Its timing simply agrees with the memory. As such, this MRAM has no such signal.
To further complicate matters, the diagrams prior to page 12 for examples of the minimum/maximum mode hardware configurations only show READY being used by the clock and reset generator logic, but the memory and local bus is not utilizing it whatsoever.
So, final question being, is this line even necessary for memory access? Am I even getting its function correct? Please advise.
