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I have tried to implement the example design which provided with "Virtex 6 Embedded Tri-mode Ethernet MAC wrapper v2.3" in Core generator,on virtex 6 development board(ML605) When I program it on the board , the packets were successfully received by the FPGA,but the board is not transmitting back the packets.I am using "Wireshark" for analysing the packets and packETH for transmitting the packets.

Please Help, I am confused...

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2 Answers 2

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Currently I'm not allowed to write my questions as a comment ... so I'll write it as an answer and try to develop a solution.

  1. Have you checked if the PHY is receiving your TX clock?
  2. Have you connected ChipScope to the I/O flip flops incl. valid and error bits? If not, please capture all outgoing data to the PHY?
  3. Is your PC with WireShark directly connected to the FPGA or is there a switch, router, ... in the middle?

How to capture low-level Ethernet packets with ChipScope

Your example design was generated with a GMII interface module called gmii_if.vhd (or gmii_if.v if you are using Verilog). Please connect a 20 bit wide and - lets say - 4096 samples deep ChipScope ILA to the following signals:

  • TXD_FROM_MAC
  • TX_EN_FROM_MAC
  • TX_ER_FROM_MAC
  • RXD_TO_MAC
  • RX_DV_TO_MAC
  • RX_ER_TO_MAC

Add TX_EN_FROM_MAC and RX_DV_TO_MAC to a trigger port (trigger type: basic with edges). Capture all data with the appropriate 125 MHz Ethernet clock. Now synthesize your design and connet the ChipScope Analyzer to the FPGA. Set up a trigger on the signal RX_DV_TO_MAC with the condition rising edge ('R'). Arm the trigger and send some test data to the board. If your PHY is working correctly you should see the ethernet frame on RXD_TO_MAC. Now you can redo this procudure with a trigger condition on TX_EN_FROM_MAC.

If there is no data coming in, I would guess that you did not drive the PHYs reset wire correctly -> it's low acive. Please check this, too.

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  • \$\begingroup\$ My setup: I directly connected the board to PC via an Ethernet cable,regular one (cat 5 or 5e not sure). I set the jumpers ,programmed the board and tried to run it. Didn't use any switch in between . I am using GMII mode.But when am transmitting the packets ,An Led near the Ethernet port in the board blinks.I did not see any transitions in the ChipScope,even in the clock.How to check whether PHY is receiving TX clock or not ? Thanks in advance \$\endgroup\$
    – Nijil Kadavathu Valapil
    Commented Sep 2, 2014 at 4:44
  • \$\begingroup\$ @NijilKadavathuValapil Sorry I missed the notice that you replied to my answer. The Ethernet PHY has a management port called MDIO, this port can be accessed via MDIO protocol if the chip is onboard and via I²C if the chip is mounted in a SFP cage. MDIO supports up to 1 MBit/s communication transferring 16 bit words. If MDIO is responsive then the PHY is active. Then you can check the internal configuration and status registers to read errors, external link speed, auto neg. parameters, ... . I think this could be one method to determine the PHY's state. \$\endgroup\$
    – Paebbels
    Commented Oct 4, 2014 at 10:24
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The issue was with the link speed of the PC. I changed the speed of the PC to 1Gbps, the board is transmitting back the packets.

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