I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * \$\2^{18}\$ memory array whose code is as follows:
//The 32x2**18 MEMORY CHIP
module mini_sub_chip (word_out, word_in, word_addr, cs, we, clk);
parameter WIDTH = 32,
DEPTH = 1 << 18,
SEL_BITS = 18;
//output
output reg [WIDTH-1:0] word_out;
//inputs
input [WIDTH-1:0] word_in;
input [SEL_BITS-1:0] word_addr;
input cs, we, clk;
//regs
reg [WIDTH-1:0] schip [0:DEPTH-1];
always @ (posedge clk)
begin
if (cs)
begin
if (we)
begin
schip[word_addr] <= word_in; // write into memory
word_out <= word_in;
end
else
begin
word_out <= schip[word_addr]; //read from memory
end
end
end
endmodule
I then tried to increase the memory width to 512 by creating 16 instances of the above module in a different module as follows:
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else
count <= count + 1;
word_output <= word_out[count] //word_output is the 32 bit output register
end
decode_4x16 dcd416 (sel, count);
generate
for (i = 0; i <= 15; i = i + 1)
begin: loop
assign chip_sel[i] = cs & sel[i];
mini_sub_chip mschip (word_out[i], word_in, word_addr, chip_sel[i], we, clk); //Instantiating 16 modules in parallel
//word_out is 32x16 array, with a different 32 bit array element driven every time 'mini_sub_chip' is instantiated
end
endgenerate
At every clock cycle, a 32-bit data is transferred from every instantiated module in a consequtive manner such that it takes 16 clock cycles to complete the 512-bit data transfer.
The first module is working correctly, but the second module is not. Data is being written to and read from memory correctly at every clock cycle, but the 'word_output' register is not getting updated as long as memory write is taking place. So it remains undefined for as long as 'we' is asserted. However, it is getting updated during memory reads. Please guide
