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Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a divide-by-8 clock based on an input clock. It works fine as long as the input clock is stable.

But now i sweep the input clock at every 90 us by +/-5%. I see that although the DCM does not lose lock, it takes very long (15 to 20 us) to change the output freq after changing the input frequency. This is for me undesirable. Any suggestions?

This question was posted on the Xilinx forum and the suggestion was to reset the DCM everytime it loses lock. But the problem is that the DCM is not losing lock.

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  • \$\begingroup\$ try using one of the PLL primitives. \$\endgroup\$
    – davidd
    Commented Jan 27, 2015 at 16:52
  • \$\begingroup\$ PLL is better then DCM for varying frequency input? \$\endgroup\$
    – Sai Gautam
    Commented Jan 28, 2015 at 9:05
  • \$\begingroup\$ This question refers to the analog parts of an FPGA and should IMHO be posted on EE-stackoverflow. It is also a cross-post from the Xilinx Forum and it would be polite of you to at least (a) be clear about that and (b) repeat the relevant inputs you got there already here! Also a linkt to the specs/datasheet of the specific FPGA and its DCM would be helpful. \$\endgroup\$
    – mbschenkel
    Commented Jan 28, 2015 at 12:17
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    \$\begingroup\$ @mbschenkel i have taken your suggestions and edited the post. Thank you \$\endgroup\$
    – Sai Gautam
    Commented Jan 28, 2015 at 12:34

1 Answer 1

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I'm not into Xilinx and don't know much of its internal structure. However, if you need just to divide input clock by 8, you can make it on logic (some simple counter) and then inject output of final flipflop into clock network of your Spartan chip.

From the general point of view, PLL also can fail in tracking heavily or abruptly varying input clock.

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  • \$\begingroup\$ how can i use counter logic to generate a faster clock? also, how can I handle varying input with counters? \$\endgroup\$
    – Sai Gautam
    Commented Jan 28, 2015 at 12:26
  • \$\begingroup\$ You have just said "to generate a divide-by-8 clock", so you can easily divide clocks (make clock's period greater) in logic. Of course it is near to impossible to multiply clocks (make period shorter) in logic. The counter will just increment on every positive (or negative) edge of clock, it won't care of a clock frequency, until it is fast enough at all to handle some faster clock. \$\endgroup\$
    – lvd
    Commented Jan 28, 2015 at 13:21
  • \$\begingroup\$ @lvd...yea this is the problem. My input clock frequency is 13.56 Mhz and i expect an output of 13.56x8=108.48Mhz. In general lets say Fin is the input freq, Fout is the output freq- Then Fout = 8xFin and Fin varies at Fin+/-5%. Thats the reason I use DCM. The problem is that the DCM is taking too long to change Fout when Fin changes. \$\endgroup\$
    – Sai Gautam
    Commented Jan 28, 2015 at 13:44
  • \$\begingroup\$ @SaiGautam: Have you evaluated to use dedicated PLL / VCO ICs instead? A part that is made for this purpose will be more likely to provide the dynamic response you need than an FPGA which is made for constant frequency inputs and mostly synchronous digital logic. \$\endgroup\$
    – mbschenkel
    Commented Jan 29, 2015 at 12:15
  • \$\begingroup\$ @mbschenkel I tried to use PLL but unfortunately the Fmin for the PLL is 19Mhz whereas I am operating at 13.56Mhz +/- 5% \$\endgroup\$
    – Sai Gautam
    Commented Jan 29, 2015 at 12:30

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