How to pass a signal from one module to another using dot operator in verilog

Question

I have got a memory module which consists of a memory

module memory(clk,rst,addr,data,wrt,rd); 
reg [7:0] mem [254:0];

I am using this memory module in the execute module and I want to use the memory without replicating it again in the execute module.

module execute(decoded_instr,clk,rst,instr_in);
if(instr_in[3:2] == 2'b00)
      PR = mem[AR];
    else if(instr_in[3:2] == 2'b01)
      DR = mem[AR];
    else if(instr_in[3:2] == 2'b10)
      GR = mem[AR];

One method is to copy the content pointed by the register AR into a temp register in the memory module and use this temp register in the execute module like

temp_AR <= mem[AR];

and tie temp_AR in the execute module and use temp_AR like

      PR = temp_AR;

My question is, is there a way to perform the same operation using dot operator and access the memory?

Thanks in advance

Answer 1

Your approach would not be synthesizable (ie., would not translate into real hardware). You don't want to use a backdoor to your memory array, it's like adding read ports that don't exist.

I'm guessing you are trying to build a pipelined implementation. At cycle 1, read the memory content at address AR. At the next cycle, decode the value you obtained and assign it to PR, DR or GR depending on the decoding. Notice how you don't have to read it again from memory, you already saved it at the previous cycle.