Balancing Rise and fall times at input and output in CMOS Design

Question

How do I make sure that my rise and fall times are balanced between input and output in a CMOS design?

Simulation of your design in whatever process node you're using. — horta, Commented Apr 1, 2015 at 5:03

Zulu · Accepted Answer · 2015-04-01 19:24:51Z

1

Scale your pull-up PMOS circuitry to have the same conductance as the pull-down NMOS circuitry. For an inverter, this means scaling the PMOS to be 2-3× wider than the NMOS, because holes are 2-3× less mobile than electrons.

answered Apr 1, 2015 at 19:24

Zulu

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