High PCB copper thickness: What are the pitfalls?

Question

We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns (1 oz) in our designs, so 'high thickness' for us means, 70 (2 oz) or 105 (3 oz).

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1. It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2. Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3. If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4. About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5. When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

Answer 1

I'm late to the game, but I'll give it a shot:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.

Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).

Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.

Answer 2

If only fraction of traces need 30A, I would still suggest to solder copper wire on top of the trace. This might even be cheaper to manufacture, as you are not using any 'rare' materials (like 100\$\mu\$ Cu). 2mm\$^2\$ copper wire is dirt cheap and much more robust than thin PCB trace.

Is this current DC? With AC current you might be limited by skin effect.

Answer 3

I think 105\$\mu\$ is the thickest you can get, but I can see no reason why you wouldn't get it on inner layers. A PCB is just a stackup of epoxy, copper and glass fiber. You can play with thickness at will. Thicker inner layers won't be as efficient, of course, since they can't give off their heat to the environment easily; the epoxy is a poor thermal conductor.
We had a design which demanded 16A over several traces, and ended up with 4mm traces top and bottom, and big diameter vias on them from beginning to end. No inner traces, I don't recall copper thickness.

Answer 4

I think the #1 unexpected gotcha may be: The PCB fab marketing people advertise that they can fab very tight trace/gap widths, and also advertise that they can 35, 71, and 105 um thick copper (commonly called 1, 2, and 3 ounce copper), but they can't do both on the same board. If you want thicker copper, you must space traces further apart than you may be used to on more typical PCBs.

1. You can always call a PCB fab and ask if they can handle thicker copper. But be sure and ask how much that will cost. Even if they can make thicker copper, you may not want to pay the cost adder.

2. The copper on the 2 outer layers is always thicker than the inner layers. PCB fabs typically buy "blank" copper-clad boards with 17.5 um or 35 um thickness, etch them and add spacers between them and glue them together, so that's the thickness of every internal layer. Then they drill holes and toss the PCB into the plating bath, which grows a layer of copper in each hole and on the outer layers. The result is that all inner layers have the same thickness, and both outer layers have the same thickness, thicker than the inner layers.

3. When pushing high currents, you typically want wide, short traces to reduce the resistance and hence the I2R heat generated in those traces. If you have 2 unequal traces on different layers "in parallel", reducing the width of any part of either trace increases the resistance and hence the I2R heat generated, making things worse -- it doesn't matter if you make the board more balanced by reducing the width of the wider trace or more unbalanced by reducing the width of the narrower trace.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

I suspect that placing the array close to the current source will give a lower net resistance.

"Are there any problems having asymmetrical copper weights? E.g. 35 um on layer 1-4 and 70 um on layer 5 and 6?"

Early PCB fabs had problems unless the layers were "balanced". My understanding is that modern PCB fabs no longer have those problems, so people could in principle make unbalanced PCB. But most people don't bother -- the standard thin-internal layers, thick-external-layers, with 2 distinct thicknesses, is often adequate for most boards.

Answer 5

The best source for many of these questions is the PCB vendor that you have selected. Different PCB vendors excel at different types of boards: some are great at high speed, tight tolerances; others are good at high power applications. Most will do just about anything you ask, but there may be a price premium.

You didn't mention whether the high current will be at high voltages. If so then you will have additional creepage/clearance requirements to meet in order to pass product safety requirements.

Answer 6

1.It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

There are a much smaller number of board houses that can do more than 3oz. But if you design your board that way you may be stuck using them forever because there won't be a lot of other options. I would stick with 3oz at most.

A lot of board houses can do 3oz copper. But keep in mind that many board houses don't keep the 3oz copper material in stock. So if you use it you may have to wait an extra week or two for them order the material. This has typically not been too big of a problem in my experience as long as you plan for it in your project schedule.

2.Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

Its usually the opposite.

If you are going to put any SMD components on the board then its likely your outer layers will still be 1oz and some of the inner layers will be 3oz.

3.If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

It is both preferred and possible to distribute the current equally between the layers, but there is no requirement.

The calculations are a lot easier when every layer is the same.

The best way to do that is to make sure that the current carying shapes on all layers are identical. Also the layers should all be tied together at the source and destination, either by a grid of vias, a plated through hole, or both.

But if you have space on some other layer then by all means use the extra copper, it will only reduce the heat.

4.About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

I have used the IPC recommendations for trace width without problems. But if you have high current on multiple layers expect the temperature rise to be higher for a given ammount of copper (so use more copper if you have space).

Also its worth estimating the trace resistance. If your cad tool can do this then great, if it can't you can just estimate the number of copper "squares" from one end to the other. The resistance is typically 0.5m Ohms per square at 1oz or 166u Ohms per square at 3oz. Using the current and the resistance calculate the trace wattage. Check that the wattage seems rasonable before proceeding.

Also don't forget wattage generated by connector contacts, crimps, solder joints, etc. Those things all add up when dealing with high current.

5.When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

It depends on if your source and destination are surface mount or through hole.

If through hole then the plated hole already ties all the layers together so thre may be no need for extra vias.

You want the current to be on as many layers as possible for as much as the route as possible. So for SMD pads there should be vias near the source and destination. Ideally you would put filled vias right in the pad becasue otherwise you would be running all of your current on just one outer layer until you reached the first vias.

Placing any vias away from the source and destination means that some of the current is going to flow on fewer layers for a portion of the route. If you place vias evenly along the whole path its likely that most of the current will go through the first few vias (possibly heating them up a lot) and then less current will go through the vias that are farther away. Therefore you won't get very efficient use out of those vias, and you will need more vias overall with this approach. Since vias take away from routing space it may increas the size of your board overall.