waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

Question

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm also easily convinced that trace length-matching matters when you're talking about 8cm traces or passing through a DIMM connector.

However I'm not convinced that trace-length matching is terribly important in a highly-optimized layout where you've got a memory chip butted directly up against the ASIC/FPGA that controls it, and the traces are all less than 1.5cm long. In a situation like that the "wiggles" required to match trace length will significantly increase the floor on the equalized trace length, probably doubling it.

Does anybody have actual scope plots showing the improvement, if any, gained by trace length matching when all traces are less than ~1.8cm long?

Of particular note the highest-speed memory standard (GDDR5) explicitly abandoned trace-length matching since it requires the component be on the same board as the controller (no DIMMs) and located very nearby. The JEDEC spec explicitly instructs board designers not to match trace lengths, but rather to minimize them independently instead.

Answer 1

Trace length matching is important in DDR, DDR2 and DDR3, but the most important question is how closely do they need to be matched.

For DDR1, 2 and 3, each byte should be matched to the strobe, and the strobe needs to be matched to the clock. Address and control likewise have a relationship to the clock. Just how tight the matching is depends on your specific implementation and requires you to analyse the link timing budget (See Micron note TN4611). How tightly each match is to another group of a byte depends on whether you have multiple clocks available. Once more, this is part of the timing budget analysis.

DDR3 is somewhat easier to route than the earlier versions (due to a feature known as Write Levelling), but that does not mean you do not need to do a timing analysis.

If you are using an FPGA for the memory controller, keep in mind that the effective length from the pins or balls to the die can be measures in inches rather than a few thou, and this needs to be accounted for in the timing budget (some FPGA tools normally allow timing closure to take care of this internally, but you need to enable the feature. Not all tools can do this).

So - can you ignore the track length match for DDR itnerfaces? My answer is no; you can however, do no more length match than a shortest route provided it does not violate the timing margin for the interface.

I will note that the timing budget becomes easier to meet the shorter the interface; the timing budget is dominated by read timing which has both an outbound and inbound component. The shorter the interface, the lower the cumulative timing offsets.

Answer 2

I'm working on a design now with the same situation: the DDR3 traces all want to be less than 2cm and length matching will increase the length.

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For DDR3 each group of 8 data lines is a "byte lane", with a dedicated strobe. All 8 bits are latched in at the same time.

Assume speed of light propagation for the back of the envelope calculation. So maybe 33ps per centimeter for the signals. The DDR3 clock could be 666Mhz or a clock edge every 750ps. If your clock signal is 1.8cm shorter than the worst data line, it will arrive close to 60ps before the data bit.

Now 60ps out of 750ps is 12% of the period, which does not seem so bad. But I am not qualified to comment on how this might affect system reliability.

See also "Freescale AN3940", which recommends matching via count in addition to trace length. It does not directly address the issue of a single DDR3 chip with short traces.

The total time budget, including everything, seems to need to be within 110ps, per Micron: