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This is my re-designed layout. What is your view again?
10-32V to 5V 1.2A SMPS Buck Regulator Design. The IC is IFX91041 from infineon.
Here are the schematics and layouts: http://www.mediafire.com/?69e66eje7vda1
(I was given 45 cm² (~6.98 inch²) area for both 5v 1.2A and 35V 4A.)
I agree with the other answers here but just thought this may help:
I've drawn the 2 high current / high switch frequency loops of most concern in this design.
Green shows the input current loop with the C7/C18 decoupling caps sourcing most of the high frequency current needed. This loop is very large due to poor ground design.
Yellow shows the output current loop, it is also very large.
Perhaps most concerning is that the return currents from both the input and output to the regulator share a single ground return path through the narrow trace leaving C17.
Your ultimate goal here is to minimize the loop area of both of these loops. When doing so remember that high frequency currents, those which are the EMI concern, will follow the path of least inductance to ground, not the path of least resistance.
For example, I've drawn these paths a little wide for clarity but in reality the high frequency components of the ground return path for the output current (yellow) will try to travel directly under the input current path if it can. Its more likely to bend over under L2 on its way back.
EDIT: Update for full ground plane.
Here is an updated drawing of the current loops for your new layout:
This is much better, the ground returns are separated for clarity but the high frequency content will travel along the ground plane as close to directly under the power traces as it can. I added the feedback path in pink and lighter color denotes current traveling on the ground plane.
A few notes:
The paths are still much longer than they need to be. The feedback loop especially is quite long and will travel under the input current. This input is high impedance so any inductive coupling on this trace will have a relatively large impact on your regulation accuracy. You do cross at almost 90 degrees which reduces coupling but the ground currents do not and are an issue for other reasons (see below).
The input power trace crosses a split in the ground plane where the trace for the feedback loop runs. Never ever, ever, cross a split on a ground or power plane on an adjacent layer with a trace that has any chance of carrying high frequencies (which means any trace at all really). This creates a radiating loop as indicated by the light green return path. The end result is a large EMI problem.
I don't know if it is a result of the export to pdf or what but you seem to have lots of vias that will have clearance issues. They are too close together and too close to the component pads. Even with solder mask over the vias the solder mask clearance on the pads looks like it will expose some of the vias causing soldering issues if you use reflow. The vias near D1 for instance will almost certainly be exposed and when the board is reflowed the via will suck all the solder away from the pad leaving D1 either unsoldered or very poorly soldered.
Some vias also don't appear on both layers, such as those under U1.
What I would do:
Setup your PCB design software design rule checking with whatever clearances are required by your PCB fabricator. This will alert you to issues with via-via, via-pad and via-solder mask clearance issues.
Tear the design up and start fresh with component placement knowing that you now have a solid ground plane. Concentrate on minimizing the length of the critical paths and use as much copper as you can for these paths (bar the feedback loop, its low current). If space / layout allows, a ground pour on the surface isn't a bad idea, just make sure you can do it properly. (no orphaned copper, well coupled to the ground plane)
Edit 2:
Not sure if you have this already but here is the reference design / app notes from infineon for a 2 layer board using a solid ground plane on the bottom. They use a fairly long FB trace but keep it well clear of of the dangerous loops.
There are two high current switching loops in this (and most other SMPS designs) which you need to take care of for sufficient efficiency and low EMI noise.
Pin8 - C9 - GND
This loop will have to cover your input power.
To keep the loop itself smaller connect the capacitors ground to the groundflag of you regulator, just rotate C9 90° CCW.
What I'm missing in your design is some small but fast capacitor, like a 100-220nF ceramic capacitor. Connect it very close to the Regulator IC.
Pin 6 - L2 - C13
This will be your output loop.
Move C13 and C17 to the bottom, connect their grounds to the groundtab of the IC (use a nice big polygon fill for that.
Add a small ceramic capacitor again.
Rotate L2 180° make a nice large connection (again, a polygon fill would be the best) to C13, C17 and the IC.
Rotate D2 90° and place it between L2 and the IC., connect it to the polygon and the groundtab.
In general:
I would use the adjustable output voltage version of the part rather than the 5v part. But even if the 5v version is used, you should include the feedback voltage divider (just use a zero ohm resistor for the high side, and don't install the low side resistor). This will give you more flexibility in the long run, just in case you need a different voltage.
In general, your traces are not wide enough. Most critical will be the trace from C9 to U1.7-8, anything connected to U1.6, L2 to C17/C13, and GND between U1 and everywhere. These are the nets that will have lots of switching currents and you want to make sure they are short and wide.
U1 could be dissipating some heat, and the connection you have to the GND pad on the bottom of the part isn't going to be enough. You should increase the size of the GND plane on the top side of the PCB. Do this by moving R1 & C1 so the GND plane can expand out from under the chip.
It's hard to tell, but I don't think that you have GND connected between the top and bottom half of the circuit. You really should just have one solid ground plane under the entire PCB and not try to do anything fancy to isolate the different sections. (Exception: you still want the GND plane to cool U1, just use vias to tie that plane to the overall GND plane.)
Conclusion: Thicker traces, better cooling, lots of GND.
Edit: Here's my comments for Rev B...
The bottom should be one complete GND plane. Not split into two halfs. This is critical and should not be ignored.
When possible, don't have GND traces on the top layer-- that's what the GND plane is for. This is especially true for the GND between J1, D1, and C17.
Also, the GND trace to C8 makes that cap completely useless. The trace inductance is going to be huge. Instead use a couple of vias to the GND plane directly at the cap. C8 should probably be located next to C9.
The traces linking the top and bottom half of the circuit are way too thin. Double or triple them. Or better yet, use a copper plane/shape/fill/whatever.
The single trace on the bottom side (from C17 to U1) should be rerouted so that it is mostly on the top of the PCB. This will help keep the GND plane on the bottom more intact and less likely to do bad things.
It's hard to tell from your pictures, but you might need more vias from the GND pad/plane on U1 to the GND plane on the bottom layer. Getting more of the heat to the bottom layer is good.
The GND plane on the top layer that is connected to D2 and goes under L2 needs more vias to the GND plane on the bottom of the PCB. Put at least 2 vias under L2, and maybe a third in the lower right corner.
