How are FPGA's configured when operating independently?

Question

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using those two together, but the problem is the way we learned to use the FPGA in class involves loading the VHDL design through Quartus every time, the file seems to be lost without continuous power.

I asked around and someone mentioned that in an embedded system, the .pof or .sof would be saved onto an external memory and the FPGA reprogrammed on startup. Can someone explain what the process behind this is? Do I need to build a JTAG programmer circuit or use a microcontroller to pull this off? Can I maybe use the SD reader on the DE0 board to hold the .pof instead of buying an EEPROM chip? Are there resources available to learn how to do this?

Answer 1

Refer to Chapter 4.1 of the User Manual, "Configuring the Cyclone III FPGA". Specifically you want to be looking at the section on configuring the EPSC4 module in AS mode.

For reference (and in case the link becomes invalid), what you need to do is power up the board, connect the USB cable as normal, and then switch the "PROG/RUN" switching into the "PROG" position - the switch is in the bottom left corner by the 7-Segment displays.

In "PROG" mode you can the upload a .pof file to the EPSC4 controller using Quartus. The file will be written into the boards EEPROM memory (you can't run it off an SD card!). Leave the board in "PROG" mode and then each time you power up the FPGA will automatically be configured from the EEPROM by the EPSC4 controller.

If you want to do a one-time program again (as you were doing in your class), you can go back into "RUN" mode and upload .sof files again - these are basically uploaded straight into the FPGA not the EEPROM, so when you power off the configuration is lost.

Answer 2

Altera makes special eproms they call "Configuration devices" that can be used to store the FPGA configuration, and will be read by the FPGA on power-up. Using these things will be discussed somewhere in the Altera FPGA documentation.