How To Hold Power ON For Some Time Without Using A Microcontroller or 555?

Question

This is my first question here, so I'm hoping for help.

I'd like to take a Momentary event and use it to turn on a device (LED, for starters to model the concept) for a minute (give or take) at a steady Current & then go off. I'll need to provide ~3v at ~.350 to ~1A (.350 most likely, 1A not-so-much) from a low-voltage DC Source.

Imagine walking up to your door, stepping on the mat (with a pressure switch under it), and having the porch light come on for a minute without using your hands and you'll get the concept. With a minimum component count and all (other than wiring) in as small a package as possible. EDIT: I'm trying to build a proof-of-concept prototype as described, but the end result will be human-wearable.

I've been playing with Monostable Multivibrator ideas ("one shot" being irresistible), but seem to have hit some saturation point in my soggy melon & can't get a steady current while ON.

There's more to this project, but this specific part is scrambling my brain & I fear I'm down a rabbit hole & need expert help digging back out.

Currents, voltages & time are approximations, but my primary concerns are NOT using a microcontroller or 555, holding the Output steady during the entire "unstable state", using no or minimum quiescent current during the "stable state" (not that a one-shot is the right answer!) and keeping the bounding box as small as possible as well as keeping the cost at a minimum.

No need for complexity, just a simple trigger-and-hold-for-a-minute latch. EDIT: I'd like to emphasize the need for brutal simplicity. And that a quick momentary bump would hold non-TTL current to the load for about a minute.

I hope some creative electronics genius reads this and can suggest some possible circuit(s) to try.

Thank you for reading, and more-so for answering with a simple circuit or a link to a page with one on it.

J

Answer 1

Your goals are contradictory.

my primary concerns are NOT using a microcontroller or 555,

Okay. Not a real engineering goal but maybe an interesting goal for learning from. You'll find lots of monostable circuits online if you just google image search for them. It's also still possible to design digital logic from single gate building blocks.

holding the Output steady during the entire "unstable state"

You can probably solve this by using a buffer between the logic circuit's output and the load. The buffer might be a simple as a single MOSFET.

using no or minimum quiescent current during the "stable state"

Almost certainly the best way to do this is using a microcontroller instead of a monostable. Many microcontrollers can enter a very low power sleep state, and then respond when they receive an interrupt (for example due to a pressure switch being activated).

for a minute (give or take)

It's generally tricky to get a monostable to keep time accurately over such a long period. Again, the low power, low cost solution is likely a microcontroller. You could also design a digital circuit using discrete logic (start with a counter), but it will almost definitely consume more quiescent power than the microcontroller solution.

A general tip: When you're designing something for an application you've never tried before, first make a working design --- just one that has the basic required functionality --- then once you know how that performs start thinking about how to optimize it for speed or power or whatever's important in that application.

Answer 2

How long do you want the light to stay on for? Are you willing to tolerate a slow decay?

You can do a simple delay timer using nothing more than a MOSFET and a RC network on the gate. But there are a few caveats and one subtlety.

You want to use a MOSFET with a low threshold voltage, then charge the timing capacitor on the gate to a relatively high voltage. This will keep the MOSFET fully enhanced for the majority of time, then the light will decay to full off some time later.

The first caveat is that the MOSFET must be both large enough and with enough heatsink so that its temperature does not get too high while the MOSFET is in the linear region. Your power level is fairly low, so this shouldn't be a problem.

The MOSFET need to have a low threshold voltage. Head over to Digikey and search for "Trench FET". These have very low threshold voltage and are ideal for this application.

You need to charge the timing capacitor to a fairly high voltage - 12 Vdc is ideal. You mention that you have a 3 Vdc supply for the LED. Because the timing current is so low, you could put a standard 9V battery in series with the 3 Vdc supply to get 12 Vdc. The battery will last for several years but does need to be replaced when the timer period starts to get too short.

Simple sketch follows:

^{simulate this circuit – Schematic created using CircuitLab}

The FDP8880FS-ND costs about a dollar and has a gate threshold near 3V. It should be fully enhanced at about 4 Vdc or so.

When the pressure switch on the mat closes, it charges up C1. The FET turns on hard and the light goes on. C1 remains charged so long as the switch is closed.

When the switch opens, the capacitor begins to discharge. However, the FET will remain saturated until the voltage drops down to somewhere between 3 to 4 Vdc. The light will then slowly decay until it is fully off.

C1 must be a quality capacitor. Ceramic or Film is good, electrolytic is bad. Increase the value to give you the time delay that you want.

[Edit]

You want faster decay time, so the addition of M2 and R3 should do that for you.

This is untested but it should work. In operation, M2 serves to rapidly discharge C1 whenever it is turned ON. It is turned ON whenever M1 is not fully enhanced.

Circuit operation is as follows:

Assume that the circuit is OFF. M1 is OFF, as is the load. M2 is fully enhanced and places a 10k resistor across C1.

When the switch closes, R2 charges C1 to the full 12 Vdc from the two series-connected batteries. R2 is so much smaller than R3 that R3 has almost no effect on M1's gate voltage.

M1 turns on hard and the gate voltage on M2 drops to about zero. M2 turns OFF and remains that was so long as M1 is fully enhanced.

When the charge on C1 decays to the point where M1 starts to turn OFF, M2 turns ON and rapidly discharges C1.

One final advantage of modifying the circuit this way: MOSFET M1 no longer needs to spend significant time in the linear region. It can now become a physically much smaller package not needing any heatsink.

Answer 3

Try this one. you can adjust the "VAR1" to change on time. To further increase/decrease change capacitor (C1) value.

I have uploaded Proteus simulation file.

Answer 4

maybe something crazy like this:

^{simulate this circuit – Schematic created using CircuitLab}

Reading from left to right:

R3 is a potentiometer which you can tune how sensitive the pressure is required to trigger the logic change from the Force Sensistive Resistor (FSR) becoming lower resistance when pressure is applied (person steps on front mat).

An inverting buffer with schmitt trigger is used to turn that signal into digital goodness. The digital signal will go "HIGH" when someone steps on the pressure pad. The high signal goes into the S input of the "CHARGE" SR latch. The R input is connected over at the DISCHARGE SR Latch which should be off at this point.

The output of CHARGE goes high (Q = HIGH), and NOT Q will be LOW. LOW turns ON the P-Channel MOSFET shown as M1, which is normally held OFF when NOT Q is force high, or during a tri-state condition the resistor R6 is there for reliability.

When M1 turns on, current from the 3V supply flows directly into a 100uF capacitor. This node/rail is being monitored for a logic HIGH by the "RDY" (meaning ready) and "NRDY" digital buffers. When the capacitor node is READY, the DISCHARGE SR latch jumps into action, disabling the CHARGE input latch by putting it's R input high, and then turning on the low-side N Channel MOSFET M2. M2 allows the capacitor C1 to drain through a known resistor R8, forming an RC network with a time constant of ~1 second.

The charge state will go from ~2.3V (when the signal to RDY was valid) down to ~1V to be logic LOW, making the DISCHARGE SR latch reset and stop, and release the R from the CHARGE input SR Latch, allowing a new pressure step cycle to begin.

Honestly I whipped this up in about 15 minutes and there are some real-world issues such as possible race conditions, un-equal schmitt trigger thresholds all over the place, and the need for probably at least 2 more RC-networks to slow down signals on purpose and avoid these race conditions, especially for RDY and NRDY.

both MOSFETs would need to be very low voltage logic level MOSFETs, i'd go for 1V Vgs_th values, and probably a 12->20V VdsMax.

All of this should work without an issue at 3V. Especially if you use CMOS logic chips and use MOSFETs as suggested. Using PNP and NPN BJTs instead of the FETs could be done, but you'd lose way too much voltage and too much current just to saturate them to reduce the forward voltage drop. All of these CMOS devices will have ultra low leakage/quiescent current too.

In terms of solution size, you can do surface mount 0402 size passives, get a dual SR Latch IC, a P and N complementary MOSFET package which is probably a tiny SOT23-6, and a single hex inverter buffer + Schmitt trigger output style logic chip (such as the Texas Instruments SN74LV14ADR), and the "non inverting" buffer is just two inverters chained in series, which is great because then you use more of the available circuits in that package.

If anyone could add to this circuit or expand on the theory to make it more robust, please feel free to comment!