i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes:
- I am using 3.3V VCCIO for all IO banks. I misread the handbook and connected TMS and TDI pins on the 3.3V VCC instead of 2.5V VCCA. After realising this, i corrected it but it might be too late. Would this be enaugh, to fry the JTAG?
- After soldering the chip in place, i failed to notice in time there are about two to five solder bridges between pins. Some of them shorted my 3.3V VCC. After i realized this, i reworked the chip and triple checked for any bridges. There are not any.
- Because of the problems mentioned above, i had to solder and desolder the chip twice. I was using hot air station. I tried to controll the temperature as well as i could (with thermocoupple right on top of the chip) but i did it by hand. Could it be damaged by the heat?
When i connect the board to the USB blaster, quartus says that it could not initiate JTAG chain, because no devices were found. I tried debugging the jtag using oscilloscope, but since this is my first time trying to do it, i do not know what exactly to look for. I noticed the following:
- When using JTAG debugger and setting how many clock pusles to send, clock signal looked quite weird. If i sent less than 8 pulses, the scope showed quite nice square wave. But when setting the clock to send more pulses, the signal became weird. There were few nice pulses as before and then there were random bursts of pulses of about 6x the frequency of the original ones. At first i thought they were just noise, but they were perfectly uniform. Almost seemed like the programmer would try to communicate on different frequencies. I do know if this is normal behavior of JTAG or not.
- The TDO pin was staying high all the time. Which i assume is a sign of broken jtag interface in fpga.
- Other pins were showing some data, but i do not know enough about the protocol to say, if it was correct.
Every VCCIO is connected to the 3.3V, every VCCA to 2.5V and every VCORE is connected to the 1.2V. Coud the problem be, that VCCIO of the bank where JTAG resides is 3.3v?
I am sorry if i forgot something or sound too stupid. This is my first fpga project so please be kind. :-) Thank you in advance for all your replies!