2
\$\begingroup\$

Many CPLD product families offer each chip in multiple packages, some of which don't bond all I/O pads out to pins. Even I/O pads which aren't bonded to pins, however, may be useful if they have bus-keeper circuits. Enable the bus keeper on a pin and it will behave as a transparent latch which samples its value whenever OE is true. In some cases, this may allow one to almost double the number of available registers (e.g. a chip with 64 macrocells could be programmed to behave as a 100-bit shift register while still having some macrocells left over). Use a few bits as a counter, have the shift register output report the state of macrocell N+2, and have macrocell N+1's output enable set while macrocell N is being latched from the data input.

Unfortunately, the only way I know of to use those extra I/O pads is to lie to the chip-design software and say I'm using the larger-footprint device, which then means all the pinouts reported by the software will be wrong for the smaller devices. Is there any clean way with e.g. a Lattice LC4064ZE-5TN48C to indicate that one is using the smaller device (so the pinouts will be correct) and yet still map functions to the pads which don't have associated pins?

\$\endgroup\$
3
  • 3
    \$\begingroup\$ This is "clever", but is almost certainly a terrible idea in something that you want to work reliably. You also might consider: if you get this to work, how are you going to handle timing analysis? The device tools are not going to treat I/O pads with keepers as registers from the point of view of placement, routing, and meeting timing constraints. \$\endgroup\$
    – wjl
    Commented Sep 20, 2011 at 18:08
  • \$\begingroup\$ It's true that bus keepers don't get recognized as registers by the simulator, which makes simulation difficult. On the other hand, provided that one enables a pin for long enough to meet the output response time spec, and disables it soon enough before it changes to meet the output float time spec, I'm not quite sure what would disrupt the value. Small CPLDs are a lot cheaper than big ones, so the cost savings from being able to use extra registers for designs that really don't need much logic with them would be substantial. \$\endgroup\$
    – supercat
    Commented Sep 20, 2011 at 20:08
  • \$\begingroup\$ Noise sensitivity is going to be a problem as well. \$\endgroup\$
    – Mike DeSimone
    Commented Oct 21, 2011 at 13:18

1 Answer 1

Reset to default
1
\$\begingroup\$

Even if you do that, those registers may not be tested at the factory. As @wjl said, don't do this. Also timing may be different between packages due to the package parasitics.

\$\endgroup\$
4
  • 1
    \$\begingroup\$ Your point about factory testing is a good one, though I'm not sure what the probability would be of failure. I guess it's possible that a factory might conceivably take dice which fail testing on some pad drivers and put them in packages that don't use such pads, but it seems more likely that a die which failed any testing would be rejected altogether. As for differences in parasitics, a pad without a bus-keeper would rely upon capacitance to hold value (and I wouldn't trust it), but a bus keeper should hold a pad state even if the capacitance was zero. \$\endgroup\$
    – supercat
    Commented Sep 21, 2011 at 16:02
  • \$\begingroup\$ @supercat: I guess it is unlikely that those registers aren't working. And don't rely on bus keepers unless your CPLD specifically says it has them. \$\endgroup\$
    – Brian Carlton
    Commented Oct 13, 2011 at 15:39
  • \$\begingroup\$ I would figure that pins may have a capacitance which varies arbitrarily from zero to the specified maximum, leakage currents which vary arbitrarily from the specified positive maximum to the specified negative maximum. In the absence of external capacitance, a "floating" pin may arbitrarily float high or low (indeed, I've seen floating pins switch state when my hand gets close). I would expect, however, that a bus keeper would be guaranteed to be at least strong enough to cover any parasitic leakage or capacitve coupling; if not, there'd be no reason to have one. \$\endgroup\$
    – supercat
    Commented Oct 13, 2011 at 15:43
  • 1
    \$\begingroup\$ The "specified maximum" is usually in the ballpark of 3 to 10 pF, which is very weak! Seriously, you are trying way too hard to be clever, and this will be a testing and reliability nightmare. If your CPLD is so full that you want to use unbonded pins as registers, then you need the next larger chip. \$\endgroup\$
    – Mike DeSimone
    Commented Oct 21, 2011 at 13:21

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.