JK flip-flop: What is the difference between clear and J=0, K=1, rising clock?

Question

I'm trying to create a Program Counter using some JK flip-flops.

I have two different way to do that:

• Use some 74LS73 (dual JK flip-flop with clear):

  

• Use both 74LS10 (triple input NAND) and 74LS00 (double input NAND):

  

Using the first integrated circuit will be easier, but this isn't the problem.

My doubt is about the Clear pin in 74LS73: I know it will reset the flip-flop but also the combination J=0 and K=1 on a rising clock edge should do it...

So, what is the difference between the Clear pin and J=0, K=1, rising clock?

Answer 1

asynchronous vs. synchronous

asynchronous is easy for resetting the flip flop at power up. It does not require a clock to reset the flip flop.

synchronous is easy for changing the output to 0 during normal operation, it requires a clock to propagate to the output.

I could imagine if you want to build a counter, you want an easy way to reset all outputs to 0 at power up. The reset pin is ideal for that, because at power up without reset the outputs will be undefined/random. With the reset pin a power on reset doesn't require the input logic gates to get more complex.