vhdl code interfacing keypad with fpga

Question

entity hex_kp is
    Port (
      coloumn : in  STD_LOGIC_VECTOR (3 downto 0);
      sevenseg : out  STD_LOGIC_VECTOR (7 downto 0);
      ca : out  STD_LOGIC_VECTOR (3 downto 0)
    );
end hex_kp;

architecture Behavioral of hex_kp is
  signal row: std_logic_vector(3 downto 0);

  process(row, column)
  begin
    ca <="0111";
    if(row = "0111") then
      case coloumn is
        when "0111" =>
          sevenseg <= "00000110";
        when "1011" =>
          sevenseg <= "01011011";
        when "1101" =>
          sevenseg <= "01001111";
        when "1110" =>
          sevenseg <= "01110001";
        when others =>
          sevenseg <= (others => '0');
      end case;
    end if;

This is one part of my VHDL code to interface keypad with Basys2. However it gives error to process(row, coloumn) part. When I exclude it it gives error to if (row = "0111") part. First I wrote row as an output but then I changed it to signal. Same errors occur in the situation row as an output. I can't see my mistake. Can anyone help?

Answer 1

Assuming `row is an input:

library ieee;
use ieee.std_logic_1164.all;

entity hex_kp is
    port ( 
        row:        in  std_logic_vector (3 downto 0);
        coloumn:    in  std_logic_vector (3 downto 0);  -- 'column 'is mispelled
        sevenseg:   out std_logic_vector (7 downto 0);  -- why is 7 segs 8 long?
        ca :        out std_logic_vector (3 downto 0)
    );
end entity hex_kp;

architecture behavioral of hex_kp is
    -- signal row: std_logic_vector(3 downto 0);  -- who drive row?
begin  -- this was missing
UNLABELLED:
    process(row, coloumn)  -- was 'column' (didn't match declaration)
    begin
        ca <="0111";
        if row = "0111" then
            case coloumn is
                when "0111" =>
                    sevenseg <= "00000110"; 
                when "1011" => 
                    sevenseg <= "01011011";  
                when "1101" =>
                    sevenseg <= "01001111";
                when "1110" =>
                 sevenseg <= "01110001";
                when others =>
                    sevenseg <= (others => '0');
            end case;
        end if;
    end process;
end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity hex_kp_tb is
end entity;

architecture foo of hex_kp_tb is
    signal row:         std_logic_vector (3 downto 0);
    signal coloumn:     std_logic_vector (3 downto 0);
    signal sevenseg:    std_logic_vector (7 downto 0);
    signal ca:          std_logic_vector (3 downto 0);
    signal count:       unsigned (7 downto 0) := (others => '0');
begin

DUT: 
    entity work.hex_kp
        port map (
            row => row,
            coloumn => coloumn,
            sevenseg => sevenseg,
            ca => ca
        );
STIMULUS:
    process
    begin
        row <= std_logic_vector (count(3 downto 0));
        coloumn <= std_logic_vector (count(7 downto 4));
        wait for 100 ns;
        count <= count + 1;
        if count = "11111111" then
            wait;
        end if;
    end process;
end architecture;

You were missing the begin for the architecture body. You also mispelled column, while spelling it correctly one place.

Your modified code analyzes, elaborates and the added testbench simulates:

Note that not having an else for the if statement based on a particular value of row causes latches preserving the value of sevenseg for other values of row.

This isn't particularly robust, `row = "0111" is a combinatoric evaluation that can cause glitches. You could consider using the result of the equality comparison as an enable to something with a clock.

You could also get rid of the latches by using an else for the if statement assigning sevenseg to some value.