FSM 4x7 segment displays Verilog

Question

I got problem getting around Verilog. I am trying to create a FSM that displays numbers on one of the displays and on the next state to display a string. I did make the string to be displayed separately and the number separately in 2 projects, but I am getting errors when I try to combine it. What I did was to set an always@ loop and place in there a flag in if else statement with two switch cases but I got error saying that is preferable to get rid of the combinatorial logic loop. Is there any way I can combine both functionalities?

Ok, I will post some code, but the main picture is that I have a master state machine and then I got another state machine. I use the other state machine as input to the 7segment display for a single number. But in a different state of the master state machine I have to display a message on the 4 7segment displays. What I got now is: Here I used CLK in order to make the message

always@(BIN_IN or CLK) begin
if(FAIL==1) begin
     case(state)
           left:
           begin
               HEX_OUT [6:0] <= F;
               SEG_SELECT_OUT <= 4'b0111;
               state <= midleft;
           end
           midleft:
           begin
               HEX_OUT [6:0] <= A;
               SEG_SELECT_OUT <= 4'b1011;
               state <= midright;
           end
//same for the rest
end
else begin  
case (BIN_IN)
4'h0 : begin
    HEX_OUT [6:0] <= 7'b1000000;
    SEG_SELECT_OUT <= 4'b0111;
end
//same logic for the other cases

Thanks

Answer 1

I think i understand your problem , i had similar problem when starting making circuits in HDL (verilog or VHDL) and coming from programming C++ , python or other languages.

What you need to understand is that in verilog , your variables represent wires(bits) or group of wires (vectors).... so you cant assign same variable as output from 2 parts of your circuit... this would be as weird as having a lamp with 2 plugs ...

Just "somehow" put both machines in same process and it will work.