FIFO in VHDL : ERROR:HDLParsers:3324

Question

I'm programming a Spartan 3AN using ISE and I would like to implement a simple code that uses a Fifo :

When I push a button, a data is sent to the FIFO and when I push another button, the fifo is read and the data is sent to the LEDs...

Unfortunately, I've an error that occurs :

ERROR:HDLParsers:3324 - "D:/.../TOP_MODULE.vhd" Line 129. IN mode Formal dout of Led_out with no default value must be associated with an actual value.

And I don't know how to change it... Here's my top module and Led_out component :

TOP MODULE :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity TOP_MODULE is
port (
        M_CLK : IN STD_LOGIC;
        BUTTON_T15 : IN STD_LOGIC;
        BUTTON_T16 : IN STD_LOGIC;
        LEDS : OUT STD_LOGIC_VECTOR (7 downto 0)
        );
end TOP_MODULE;

architecture Behavioral of TOP_MODULE is

component Data_generator is
PORT (
        M_CLK : IN STD_LOGIC;
        BUTTON_T15 : IN STD_LOGIC;
        wr_en : OUT STD_LOGIC;
        full : IN STD_LOGIC;
        DATA : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
        );
end component;

component fifo_generator_v9_3 is
PORT (
        M_CLK : IN STD_LOGIC;
        rst : IN STD_LOGIC;
        din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
        wr_en : IN STD_LOGIC;
        rd_en : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
        full : OUT STD_LOGIC;
        empty : OUT STD_LOGIC
        );
end component;
signal RESET, WRITE_EN, READ_EN, FIFO_FULL, FIFO_EMPTY : STD_LOGIC;
signal DATA_IN, DATA_OUT : STD_LOGIC_VECTOR(17 downto 0)";

component Led_out is
PORT (
        M_CLK : IN STD_LOGIC;
        BUTTON_T16 : IN STD_LOGIC;
        rd_en : OUT STD_LOGIC;
        LEDS : out STD_LOGIC_VECTOR (7 downto 0);
        dout : IN STD_LOGIC_VECTOR(17 DOWNTO 0)
        );
end component;

begin

U100:Data_generator
port map(
            M_CLK,
            BUTTON_T15,
            WRITE_EN,
            FIFO_FULL,
            DATA_IN
            );

U101:fifo_generator_v9_3
port map (
            M_CLK,
            RESET,
            DATA_IN,
            WRITE_EN,
            READ_EN,
            DATA_OUT,
            FIFO_FULL,
            FIFO_EMPTY
            );

U102:Led_out
port map (
            M_CLK,
            BUTTON_T16,
            READ_EN,
            DATA_OUT
            );
end Behavioral;

LED_OUT COMPONENT :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Led_out is
Port (M_CLK : in  STD_LOGIC;
        BUTTON_T16 : IN STD_LOGIC;
      rd_en : out  STD_LOGIC;
        LEDS : out STD_LOGIC_VECTOR (7 downto 0);
      dout : in  STD_LOGIC_VECTOR (17 downto 0)
        );
end Led_out;

architecture Behavioral of Led_out is
signal cnt : integer range 0 to 1:=0;

begin
process (M_CLK)
begin
if rising_edge (BUTTON_T16) then
    rd_en <='1';
    cnt <=1;
    if cnt =1 then
        LEDS <=dout (17 downto 10);
    end if;
else
rd_en <='0';
end if;
end process;
end Behavioral;

My question is : Can someone explain where this error come from and how to change it?

This is my first use of FIFO in VHDL...

Thanks in advance !

Answer 1

Because you asked where the error comes from.

See IEEE Std 1076-2008, 6.5.6.3 Port clauses, para 9:

If a formal port is associated with an actual port, signal, or expression, then the formal port is said to be connected. If a formal port is instead associated with the reserved word open, then the formal is said to be unconnected. It is an error if a port of mode in is unconnected (see 6.5.6.3) or unassociated (see 6.5.7.3) unless its declaration includes a default expression (see 6.5.2). It is an error if a port of any mode other than in is unconnected or unassociated and its type is an unconstrained or partially constrained composite type. It is an error if some of the subelements of a composite formal port are connected and others are either unconnected or unassociated.

This is a problem with the association list (the port map) in the component instantiation for Led_out:

U102:Led_out
port map (
            M_CLK,
            BUTTON_T16,
            READ_EN,
            DATA_OUT
            );

In 6.5.7 Association lists, 6.5.7.1 para 2 we see that the formal_part of an association is optional:

association_list ::=
    association_element { , association_element }

association_element ::=
   [ formal_part => ] actual_part

Para 4:

An association element is said to be named if the formal designator appears explicitly; otherwise, it is said to be positional. For a positional association, an actual designator at a given position in an association list corresponds to the interface element at the same position in the interface list.

So you are using positional association and the actual designator is found by the association's position in the association list (the port map).

However your component declaration:

component Led_out is
PORT (
        M_CLK : IN STD_LOGIC;
        BUTTON_T16 : IN STD_LOGIC;
        rd_en : OUT STD_LOGIC;
        LEDS : out STD_LOGIC_VECTOR (7 downto 0);
        dout : IN STD_LOGIC_VECTOR(17 DOWNTO 0)
        );
end component;

doesn't have the same number of formals as the actuals you associate by position in the port map, the port map has one fewer which means the last one (dout) is unassociated according to paragraph 4 of 6.5.7.1 positional ordering.

That last port of the port clause is mode in and that violates the rule in paragraph 9 of 6.5.6.3, an error that can be detected at elaboration time.

14. Elaboration and execution of a model, 14.3 Elaboration of a block, package, or subprogram header, 14.3 Elaboration of a port clause, para 4 (in part):

If a given port is a port of mode in whose declaration includes a default expression, and if no association element associates a signal or expression with that port, then the default expression is evaluated and the effective and driving value of the port is set to the value of the default expression. ...

So if there were a default expression provided in the port declaration the unassociated formal of port in would not have an error.

See 6.5.2 Interface object declarations, para 6 (in part):

If an interface declaration contains a “:=” symbol followed by an expression, the expression is said to be the default expression of the interface object. ...

(And there are various rules for default expressions).

You're getting an error caused by not having LEDS which id declared as a mode out port in TOP_MODULE in the association list (the port map) where Led_out is instantiated.

And as Brian comments these things become readily apparent when using named association.