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I'm connecting SRAM to FPGA (Spartan 6). During configuration and during periods when FPGA will be down (for example I would like to turn off FPGA when external flash will be programmed by uC) address lines of SRAM will not be driven, thus floating - which is bad I guess.

I came up with the idea to use a transistor to turn on / off SRAM. As I have uC on the board, I can connect base of transistor (ex. BC817) to uC and its collector to Vcc and emitter to VCCs of SRAM so I would be able to turn off SRAM when FPGA is down and when it is configured and runnign I can turn on transistor and thus SRAM.

Do you think it will be ok? Is it good idea?

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  • \$\begingroup\$ Why do you think having the floating address lines is bad (it might be bad for some particular cases, but are you sure you are having them?) \$\endgroup\$
    – Eugene Sh.
    Commented Nov 23, 2015 at 18:19
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    \$\begingroup\$ During configuration FPGA I/O pins are in Hi-Z or can be pull-up'ed to Vcc if HSWAPEN pin is used. When FPGA power is cut off there isn't even Hi-Z so RAM inputs are really floating. And I don't know if it is bad but as I far as I know, inputs shouldn't be left open. \$\endgroup\$
    – zupazt3
    Commented Nov 23, 2015 at 18:23
  • \$\begingroup\$ Is your concern with preserving data stored in SRAM? If so, turning VCC of is a bad idea. You should make sure the chip enable lines are pulled up/down to disable writing to SRAM during reconfiguration. \$\endgroup\$
    – FRob
    Commented Nov 23, 2015 at 20:34
  • \$\begingroup\$ No, I don't care about data when I turn off SRAM. I fact SRAM will be turned off along with FPGA because they use the same voltage source. So initial question is a little bit outdated ;) Now my only question is - when chip enable is high (chip disabled) - can address lines be left floating? Datasheet says data lines are in Hi-Z - but there's nothing about address lines. \$\endgroup\$
    – zupazt3
    Commented Nov 23, 2015 at 21:38
  • \$\begingroup\$ All input pins should be driven to some defined level either directly or with a pull-up/pull-down. However, leaving the lines floating temporarily with CE disabled should not result in corrupt memory contents, perhaps just increased power consumption. \$\endgroup\$
    – alex.forencich
    Commented Nov 23, 2015 at 22:59

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Most of the Xilinx FPGAs have weal pull-ups that can be active before configuration. Just tie the HSWAPEN pin to ground. Floating pins for a brief period during power-on should not be a problem.

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  • \$\begingroup\$ And what if FPGA is turned off? If I set CE (chip enable) of SRAM to high, then address lines can be floating? \$\endgroup\$
    – zupazt3
    Commented Nov 23, 2015 at 19:35
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    \$\begingroup\$ Well, leaving them floating for a short period of time is probably OK. However, if you tie HSWAPEN to ground, the FPGA pins will be pulled high before and during configuration, so the pins should never be floating unless the FPGA design leaves them floating. In which case I would think the worst that would happen is increased power draw from the SRAM and possibly corrupted memory contents. \$\endgroup\$
    – alex.forencich
    Commented Nov 23, 2015 at 22:57
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    \$\begingroup\$ Looks like the only cycle where it 'has' to be set to 1 is for write cycle 3, where the write is controlled by the LB and UB signals. However, you don't need to use that mode. Any other read or write cycle has LB and UB as 'don't care' outside of the actual operation. So just use the WE or CE gated read/write, and you will be fine to tie those to GND. \$\endgroup\$
    – alex.forencich
    Commented Nov 23, 2015 at 23:42
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    \$\begingroup\$ Ah, that's on page 9. I think it's just strangely worded. I think it should be more like "WE or CE or (LB and UB) must be high during all address transitions" as this actually matches the timing diagrams. It's a very standard requirement - the write condition cannot be commanded during an address change. A just checked a cypress datasheet for a different async sram, "R/W or CE must be HIGH during all address transitions". \$\endgroup\$
    – alex.forencich
    Commented Nov 24, 2015 at 1:33
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    \$\begingroup\$ Yep. I think that would end up being an address timed read and a we timed write. Should work just fine. \$\endgroup\$
    – alex.forencich
    Commented Nov 24, 2015 at 17:04

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