Verilog: slow clock generator module (1 Hz from 50 MHz)

Question

I wrote a clock generator module. I think the problem is in my Reg4 module. The errors are:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 Hz clock generator:

module slowClock(clk, reset, clk_1Hz);
input clk, reset;
output clk_1Hz;

reg clk_1Hz = 1'b0;
reg [27:0] counter;

always@(posedge reset or posedge clk)
begin
    if (reset == 1'b1)
        begin
            clk_1Hz <= 0;
            counter <= 0;
        end
    else
        begin
            counter <= counter + 1;
            if ( counter == 25_000_000)
                begin
                    counter <= 0;
                    clk_1Hz <= ~clk_1Hz;
                end
        end
end
endmodule   

Here is my Reg4 bit module:

module Reg4(I, Q, clk, reset);
input clk, reset;
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;

reg clk_1Hz = 1'b0;
slowClock clock_generator(clk, reset, clk_1Hz);

always@(posedge clk_1Hz) begin      
    if (reset == 1)
        Q <= 4'b0000;   
    else
        Q <= I;
end
endmodule

Can you see the problem in my code?

Answer 1

In the Reg4 module, change:

reg clk_1Hz = 1'b0;

to:

wire clk_1Hz;

Answer 2

In the 1Hz code you haven't assigned any value to the clk_1hz. Hence no value will be assigned to it. Just include assign clk_1hz = counter[24]; outside the always block.