I am using ISE to write my first Verilog code. I wrote a counter:
`timescale 1ns / 1ps
module my_counter( input clk , output reg [3:0] out);
always @(posedge clk) begin
out <= out+1 ;
end
endmodule
I then used ISE to make a testbench (added clk myself):
`timescale 1ns / 1ps
module mycounter_test;
// Inputs
reg clk;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
my_counter uut (
.clk(clk),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
#100;
end
always begin
#5 clk = 1 ; #5 clk =0;
end
endmodule
When I use ISE simulation mode, the waveform is like:
To get the proper waveform, I first set the time.
Then click the "restart" button and then "run for the time specified in the toolbar ".
Why is the output still X after several cycles of the clock?
Does it have anything to do with the comment "Wait 100 ns for global reset to finish"?
I also tried running the counter for 120 ns, but I got the same result.