Separating Two High Speed Digital ICs

Question

Previously, I've designed a PCB incorporating this ADC chip. It has a digital bus of 10 signals some of which are 40MHz.

Right now we have a four layer PCB and the ADC is connected directly to a Spartan-S6 FPGA with ~1.5" traces, running over a ground plane. The system is working well as is, despite my 0 knowledge of high-speed digital layout.

Now, however, we need to separate the ADC and FPGA into two separate PCBs. So we are going to need 10 digital signals (some 40 MHz) travelling 10". I would prefer to minimize radiation from the cable. The high-impedance ADC inputs are already shielded, but I think EMI is important to continuously consider.

Questions:

• What type of connector/cable assembly to use? The world of connectors is overwhelming to me. Are IDC ribbon cables sufficient at 40MHz? Do I need 50-ohm transmission lines? Those fancy mini-coax ribbons? Can I use something industry standard that's pre-assembled, and won't cost a fortune?
• Will my FPGA (and especially the ADC) even be able to drive the 10" cable? The logic is 3.3V levels. The ADC data sheet I'm pretty sure doesn't even mention drive strength. However in the timing section they specifiy 100Kohm load outputs.
• Do I need to modify the design other than simply replacing the direct connection with a longer cable? How much do I need to know about transmission lines in order to solve this problem? For example, I've heard people talk about the termination of FPGA signals being important.

I know SE hates broad questions... but I'm still coming up in my EE education -- so far this is the most complicated thing I've worked on.

Answer 1

40 MHz corresponds to a wavelength of 7.5 meters. So long as you limit your driving rise and fall time to avoid exciting high harmonics, you should be able to transmit over 10 inches (~25 cm) without thinking too much about transmission lines and controlled impedance.

Are IDC ribbon cables sufficient at 40MHz?

For this distance, I'd say yes. Provide as many ground lines as you can afford to to avoid cross-talk between lanes and reduce radiation and interference.

Will my FPGA (and especially the ADC) even be able to drive the 10" cable?

You can work out the capacitance of the line and check it against the FPGA datasheet to see.

Or you can just buffer with a 74LVC244 or other logic buffer part and you'll be good. I would provide a location for a series resistor at each output to allow you to increase the rise and fall times if needed.

However in the timing section they specifiy 100Kohm load outputs.

In this case (for the ADC outputs), buffering is probably a good idea.