0
\$\begingroup\$

I am developing various verilog modules with state machine for a fpga board.

  1. When i have done simulation of the modules i have used "$display" to get what is happening in the module or otherwise the status information.

  2. Now i am implementing the same modules on the fpga. As "$display" does not support in hardware i thought of using UART to send the status information to a terminal in PC or Computer.

  3. For that i am using the UART verilog model obtained from opencore.org. But at a time only one byte can be supplied to UART for transmission.

  4. But status information contains various lengths of characters such as "Test passed", "Entered reset state" etc.

  5. Is there any easy method to send variable length strings on UART port much like a $display syntax.

\$\endgroup\$
3
  • 1
    \$\begingroup\$ A state machine, sending a byte at a time. \$\endgroup\$
    – user16324
    Commented Feb 12, 2016 at 0:54
  • \$\begingroup\$ You may want to consider two state machines with a circular queue designed into a block RAM sitting in between them. This way the part of the UART logic that generates the source byte streams can queue the data at FPGA clock speeds and a slower state machine stepping at the slow UART rates can extract the data from the queue for sendiing it out. This way your primary circuits will not need to stall during the whole UART sending process. \$\endgroup\$
    – Michael Karas
    Commented Feb 12, 2016 at 1:43
  • 1
    \$\begingroup\$ Chances are this will slow your design down to the point where there's little benefit to using an FPGA. Try to get that part debugged in simulation instead. If you have to create output from the FPGA, either use one of the vendor soft logic analyzers, or try to output single tokens, ie, give each of your messages a one character abbreviation. But realize you have to give each message time to transmit before you can send another - buffering will only work if your data is bursty, not if your events continually happen faster than they can be reported. \$\endgroup\$
    – Chris Stratton
    Commented Mar 13, 2016 at 2:42

1 Answer 1

Reset to default
1
\$\begingroup\$

Yes there is, you need a state machine. Is it easy? Thats up for debate. I've written state machines that control uarts. I don't know what ports your uart has. But usually they have a data in port and a load signal. Here is an example, I'm letting you know that its possible to answer your question. Go read up on state machines in verilog. This will give you some idea of what a state machine that controls a uart could look like:

Initilze state 1) Reset Uart -goto Initialize state2

Initialize state 2) Set Control reg signals param 1 (like setting an internal register, like for baud rate) -goto Initialize state 3

Initialize state 3) Enable control load -goto Initialize state 4

Initialize state 4) Set Control reg signals param 2 -goto 1st state) Wait

1st state) Wait If load X signal == high, Go to 2nd state if you want to load X character If load Y signal == high, Go to 4th state if you want to load X character

2nd state) Put X data on load line -goto state 3

3rd state) Enable load -go back to state 1

4th state) Put Y data on load line -goto state 5

5th state) Enable load -go back to state 1

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.